SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 323

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Figure 17-3. Raising the VDDIO Power Supply
17.4.6
17.4.6.1
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Zero-Power Power-On
Backup Power Supply
Reset Cell output
Core Power Supply
Oscillator output
Oscillator output
22 - 42 kHz RC
vddcore_nreset
periph_nreset
Fast RC
proc_nreset
bodcore_in
Core Reset
Supply Monitor Reset
NRST
vr_on
Note: After “proc_nreset” rising, the core starts fecthing instructions from Flash at 4 MHz.
The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described
previously in
asserted before shutting down the core power supply and released as soon as the core power
supply is correctly regulated.
There are two additional sources which can be programmed to activate vddcore_nreset:
The supply monitor is capable of generating a reset of the system. This can be enabled by set-
ting the SMRSTEN bit in the Supply Controller Supply Monitor Mode Register (SUPC_SMMR).
If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is imme-
diately activated for a minimum of 1 slow clock cycle.
• a supply monitor detection
• a brownout detection
Zero-Power POR
Section 17.4.5 ”Power Supply
7 x Slow Clock Cycles
T
Regulator
ON
Reset”. The vddcore_nreset signal is normally
Voltage
3 x Slow Clock
Cycles
3 x Slow Clock
Cycles
6.5 x Slow Clock
Cycles
SAM4S
SAM4S
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