SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 912

• Manufacturer Part Number: SAM4S16C
• Manufacturer: Atmel Corporation

Specifications of SAM4S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 36-10. Method 1 (UPDM = 0)
912
912
Method 2: Manual write of duty-cycle values and automatic trigger of the update
UPDULOCK
SAM4S
SAM4S
CDTYUPD
CCNT0
CDTY
0x20
0x20
In this mode, the update of the period value, the duty-cycle values, the dead-time values and the
update period value must be done by writing in their respective update registers with the CPU
(respectively PWM_CPRDUPDx, PWM_CDTYUPDx, PWM_DTUPDx and PWM_SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the bit
UPDULOCK of the
allows to update synchronously (at the same PWM period) the synchronous channels:
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is read 0.
The update of the duty-cycle values and the update period is triggered automatically after an
update period.
To configure the automatic update, the user must define a value for the Update Period by the
UPR field in the
troller waits UPR+1 period of synchronous channels before updating automatically the duty
values and the update period value.
The status of the duty-cycle value write is reported in the
(PWM_ISR2) by the following flags:
Depending on the interrupt mask in the PWM_IMR2 register, an interrupt can be generated by
these flags.
Sequence for Method 2:
• If the bit UPDULOCK is set to 1, the update is done at the next PWM period of the
• If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
• WRDY: this flag is set to 1 when the PWM Controller is ready to receive new duty-cycle
1. Select the manual write of duty-cycle values and the automatic update by setting the
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the field UPR in the PWM_SCUP register.
4. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
5. If an update of the period value and/or of the dead-time values is required, write regis-
synchronous channels.
values and a new update period value. It is reset to 0 when the PWM_ISR2 register is read.
field UPDM to 1 in the PWM_SCM register
ters that need to be updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to
0x40
0x40
“PWM Sync Channels Update Period Register”
“PWM Sync Channels Update Control Register”
0x60
0x60
“PWM Interrupt Status Register 2”
(PWM_SCUP). The PWM con-
(PWM_SCUC) which
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Step 8.