SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 339

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
19. Enhanced Embedded Flash Controller (EEFC)
19.1
19.2
19.3
19.3.1
19.3.2
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Description
Embedded Characteristics
Product Dependencies
Power Management
Interrupt Sources
The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with
the 32-bit internal bus.
Its 128-bit or 64-bit wide memory interface increases performance. It also manages the pro-
gramming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system
about the Flash organization, thus making the software generic.
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Man-
agement Controller has no effect on its behavior.
The Enhanced Embedded Flash Controller (EEFC) interrupt line is connected to the Nested
Vectored Interrupt Controller (NVIC). Using the Enhanced Embedded Flash Controller (EEFC)
interrupt requires the NVIC to be programmed first. The EEFC interrupt is generated only on
FRDY bit rising.
Table 19-1.
• Interface of the Flash Block with the 32-bit Internal Bus
• Increases Performance in Thumb2 Mode with 128-bit or -64 bit Wide Memory Interface up to
• 128 Lock Bits, Each Protecting a Lock Region
• GPNVMx General-purpose GPNVM Bits
• One-by-one Lock Bit Programming
• Commands Protected by a Keyword
• Erases the Entire Flash
• Erases by Plane
• Erase by Sector
• Erase by Pages
• Possibility of Erasing before Programming
• Locking and Unlocking Operations
• Consecutive Programming and Locking Operations
• Possibility to read the Calibration Bits
100 MHz
Instance
EFC
Peripheral IDs
ID
6
SAM4S
SAM4S
339
339

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