SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 227

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
1: A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the
error.
When the processor sets this bit to 1, it does not write a fault address to the SCB_BFAR register.
This is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the bus fault
priority, the bus fault becomes pending and becomes active only when the processor returns from all higher priority pro-
cesses. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that
both this bit and one of the precise fault status bits are set to 1.
• UNSTKERR: Bus Fault on Unstacking for a Return From Exception
This is part of
0: No unstacking fault.
1: Unstack for an exception return has caused one or more bus faults.
This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still
present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write
a fault address to the BFAR.
• STKERR: Bus Fault on Stacking for Exception Entry
This is part of
0: No stacking fault.
1: Stacking for an exception entry has caused one or more bus faults.
When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incor-
rect. The processor does not write a fault address to the SCB_BFAR register.
• BFARVALID: Bus Fault Address Register (BFAR) Valid flag
This is part of
0: The value in SCB_BFAR is not a valid fault address.
1: SCB_BFAR holds a valid fault address.
The processor sets this bit to 1 after a bus fault where the address is known. Other faults can set this bit to 0, such as a
memory management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This pre-
vents problems if returning to a stacked active bus fault handler whose SCB_BFAR value has been overwritten.
• UNDEFINSTR: Undefined Instruction Usage Fault
This is part of
0: no undefined instruction usage fault.
1: the processor has attempted to execute an undefined instruction.
When this bit is set to 1, the PC value stacked for the exception return points to the undefined instruction.
An undefined instruction is an instruction that the processor cannot decode.
• INVSTATE: Invalid State Usage Fault
This is part of
0: No invalid state usage fault.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
“BFSR: Bus Fault Status Subregister”
“BFSR: Bus Fault Status Subregister”
“BFSR: Bus Fault Status Subregister”
“UFSR: Usage Fault Status Subregister”
“UFSR: Usage Fault Status Subregister”
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SAM4S
SAM4S
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