SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 197

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.8
11.8.1
11.8.1.1
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Nested Vectored Interrupt Controller (NVIC)
Level-sensitive Interrupts
Hardware and Software Control of Interrupts
This section describes the NVIC and the registers it uses. The NVIC supports:
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until
the peripheral deasserts the interrupt signal. Typically, this happens because the ISR accesses
the peripheral, causing it to clear the interrupt request.
When the processor enters the ISR, it automatically removes the pending state from the inter-
rupt (see
is not deasserted before the processor returns from the ISR, the interrupt becomes pending
again, and the processor must execute its ISR again. This means that the peripheral can hold
the interrupt signal asserted until it no longer requires servicing.
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the fol-
lowing reasons:
A pending interrupt remains pending until one of the following:
• 1 to 35 interrupts.
• A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower
• Level detection of interrupt signals.
• Dynamic reprioritization of interrupts.
• Grouping of priority values into group priority and subpriority fields.
• Interrupt tail-chaining.
• An external Non-maskable interrupt (NMI)
• The NVIC detects that the interrupt signal is HIGH and the interrupt is not active
• The NVIC detects a rising edge on the interrupt signal
• A software writes to the corresponding interrupt set-pending register bit, see
• The processor enters the ISR for the interrupt. This changes the state of the interrupt from
• Software writes to the corresponding interrupt clear-pending register bit.
priority, so level 0 is the highest interrupt priority.
pending Registers”
Trigger Interrupt Register”
pending to active. Then:
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC
samples the interrupt signal. If the signal is asserted, the state of the interrupt
changes to pending, which might cause the processor to immediately re-enter the
ISR. Otherwise, the state of the interrupt changes to inactive.
“Hardware and Software Control of Interrupts”
, or to the NVIC_STIR register to make an interrupt pending, see
.
). For a level-sensitive interrupt, if the signal
“Interrupt Set-
SAM4S
SAM4S
“Software
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