SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 489

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
26.2.12
26.2.13
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Main Crystal Clock Failure Detector
Programming Sequence
The clock failure detector monitors the 3 to 20 MHz Crystal or Ceramic Resonator-based oscilla-
tor to identify an eventual defect of this oscillator (for example, if the crystal is unconnected).
The clock failure detector can be enabled or disabled by means of the CFDEN bit in the PMC
Clock Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled.
However, if the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is disabled, the
clock failure detector is disabled too.
A failure is detected by means of a counter incrementing on the 3 to 20 MHz Crystal oscillator or
Ceramic Resonator-based oscillator clock edge and timing logic clocked on the slow clock RC
oscillator controlling the counter. The counter is cleared when the slow clock RC oscillator signal
is low and enabled when the slow clock RC oscillator is high. Thus the failure detection time is 1
slow clock RC oscillator clock period. If, during the high level period of the slow clock RC oscilla-
tor, less than 8 fast crystal oscillator clock periods have been counted, then a failure is declared.
If a failure of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is detected,
the CFDEV flag is set in the PMC Status Register (PMC_SR), and generates an interrupt if it is
not masked. The interrupt remains active until a read operation in the PMC_SR register. The
user can know the status of the clock failure detector at any time by reading the CFDS bit in the
PMC_SR register.
If the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is selected as the source
clock of MAINCK (MOSCSEL = 1), and if the Master Clock Source is PLLACK or PLLBCK (CSS
= 2 or 3), a clock failure detection automatically forces MAINCK to be the source clock for the
master clock (MCK).Then, regardless of the PMC configuration, a clock failure detection auto-
matically forces the 4/8/12 MHz Fast RC oscillator to be the source clock for MAINCK. If the Fast
RC oscillator is disabled when a clock failure detection occurs, it is automatically re-enabled by
the clock failure detection mechanism.
It takes 2 slow clock RC oscillator cycles to detect and switch from the 3 to 20 MHz Crystal, or
Ceramic Resonator-based oscillator, to the 4/8/12 MHz Fast RC Oscillator if the Master Clock
source is Main Clock, or 3 slow clock RC oscillator cycles if the Master Clock source is PLLACK
or PLLBCK.
A clock failure detection activates a fault output that is connected to the Pulse Width Modulator
(PWM) Controller. With this connection, the PWM controller is able to force its outputs and to
protect the driven device, if a clock failure is detected. This fault output remains active until the
defect is detected and until it is cleared by the bit FOCLR in the PMC Fault Output Clear Regis-
ter (PMC_FOCR).
The user can know the status of the fault output at any time by reading the FOS bit in the
PMC_SR register.
1. Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Regis-
ter (CKGR_MOR). The user can define a start-up time. This can be achieved by writing a
value in the MOSCXTST field in CKGR_MOR. Once this register has been correctly config-
ured, the user must wait for MOSCXTS field in the PMC_SR register to be set. This can be
done either by polling the status register, or by waiting the interrupt line to be raised if the
associated interrupt to MOSCXTS has been enabled in the PMC_IER register.
SAM4S
SAM4S
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