SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 914

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
914
914
SAM4S
SAM4S
Using the PDC removes processor overhead by reducing its intervention during the transfer.
This significantly reduces the number of clock cycles required for a data transfer, which
improves microcontroller performance.
The PDC must write the duty-cycle values in the synchronous channels index order. For example
if the channels 0, 1 and 3 are synchronous channels, the PDC must write the duty-cycle of the
channel 0 first, then the duty-cycle of the channel 1, and finally the duty-cycle of the channel 3.
The status of the PDC transfer is reported in the
(PWM_ISR2) by the following flags:
Depending on the interrupt mask in the PWM_IMR2 register, an interrupt can be generated by
these flags.
Sequence for Method 3:
• WRDY: this flag is set to 1 when the PWM Controller is ready to receive new duty-cycle
• ENDTX: this flag is set to 1 when a PDC transfer is completed
• TXBUFE: this flag is set to 1 when the PDC buffer is empty (no pending PDC transfers)
• UNRE: this flag is set to 1 when the update period defined by the UPR field has elapsed
1. Select the automatic write of duty-cycle values and automatic update by setting the field
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the field UPR in the PWM_SCUP register.
4. Define when the WRDY flag and the corresponding PDC transfer request must be set in
5. Define the PDC transfer settings for the duty-cycle values and enable it in the PDC
6. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
7. If an update of the period value and/or of the dead-time values is required, write regis-
8. Set UPDULOCK to 1 in PWM_SCUC.
9. The update of these registers will occur at the beginning of the next PWM period. At
10. If an update of the update period value is required, check first that write of a new update
11. Write the register that needs to be updated (PWM_SCUPUPD).
12. The update of this register will occur at the next PWM period of the synchronous chan-
13. Check the end of the PDC transfer by the flag ENDTX. If the transfer has ended, define
values and a new update period value. It is reset to 0 when the PWM_ISR2 register is read.
The user can choose to synchronize the WRDY flag and the PDC transfer request with a
comparison match (see
PTRCS in the PWM_SCM register.
while the whole data has not been written by the PDC. It is reset to 0 when the PWM_ISR2
register is read.
UPDM to 2 in the PWM_SCM register.
the update period by the PTRM bit and the PTRCS field in the PWM_SCM register (at
the end of the update period or when a comparison matches).
registers
ters that need to be updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to
this moment the bit UPDULOCK is reset, go to
value is possible by polling the flag WRDY (or by waiting for the corresponding inter-
rupt) in the PWM_ISR2 register, else go to
nels when the Update Period is elapsed. Go to
a new PDC transfer in the PDC registers for new duty-cycle values. Go to
Section 36.6.3 “PWM Comparison
Step 13.
Step 7.
Step 10.
“PWM Interrupt Status Register 2”
for new values.
for new values.
Units”), by the fields PTRM and
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Step 5.
Step 10.

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