SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 50

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.4.1.11
Name:
Access:
Reset:
The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interrupt-
ible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to
write the EPSR using the MSR instruction in the application software are ignored. Fault handlers can examine the EPSR
value in the stacked PSR to indicate the operation that is at fault. See
• ICI: Interruptible-continuable Instruction
When an interrupt occurs during the execution of an LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH,
or VPOP instruction, the processor:
After servicing the interrupt, the processor:
When the EPSR holds the ICI execution state, bits[26:25,11:10] are zero.
• IT: If-Then Instruction
Indicates the execution state bits of the
The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The
conditions for the instructions are either all the same, or some can be the inverse of others. See
• T: Thumb State
The Cortex-M4 processor only supports the execution of instructions in Thumb state. The following can clear the T bit to 0:
Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See
50
50
– stops the load multiple or store multiple instruction operation temporarily
– stores the next register operand in the multiple operation to EPSR bits[15:12].
– returns to the register pointed to by bits[15:12]
– resumes the execution of the multiple load or store instruction.
– instructions BLX, BX and POP{PC}
– restoration from the stacked xPSR value on an exception return
– bit[0] of the vector value on an exception entry or reset.
23
15
31
7
SAM4S
SAM4S
Execution Program Status Register
EPSR
Read-write
0x00000000
22
14
30
6
0
21
13
29
5
IT
instruction.
ICI/IT
20
12
28
4
19
11
27
3
“Exception Entry and Return”
18
10
26
2
“Lockup”
ICI/IT
for more information.
“”
17
25
9
1
for more information.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
16
24
T
8
0

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