SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 676
SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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31.7.1.2
Figure 31-4. Fractional Baud Rate Generator
31.7.1.3
676
676
SCK
Reserved
MCK/DIV
SAM4S
SAM4S
MCK
Fractional Baud Rate in Asynchronous Mode
Baud Rate in Synchronous Mode or SPI Mode
USCLKS
0
1
2
3
The Baud Rate generator previously defined is subject to the following limitation: the output fre-
quency changes by only integer multiples of the reference frequency. An approach to this
problem is to integrate a fractional N clock generator that has a high resolution. The generator
architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock.
This fractional part is programmed with the FP field in the Baud Rate Generator Register
(US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the
clock divider. This feature is only available when using USART normal mode. The fractional
Baud Rate is calculated using the following formula:
The modified architecture is presented below:
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 3 times lower than the
Baudrate
BaudRate
16-bit Counter
CD
=
---------------------------------------------------------------- -
⎛
⎝
8 2 Over
Modulus
=
Control
(
FP
SelectedClock
------------------------------------- -
SelectedClock
–
CD
) CD
⎛
⎝
glitch-free
USCLKS = 3
+
logic
FP
------ -
FP
8
⎞
⎠
⎞
⎠
SYNC
0
CD
>1
1
0
1
0
OVER
Sampling
Divider
FIDI
0
1
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
SYNC
SCK
Baud Rate
Sampling
Clock
Clock
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