SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 761

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
32.10.5.4
Figure 32-28. Clock Synchronization in Read Mode
Notes:
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
TWI_THR
TXCOMP
SVREAD
Clock Synchronization in Read Mode
SCLWS
SVACC
TXRDY
TWCK
1. TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been acknowl-
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
3. SCLWS is automatically set when the clock synchronization mechanism is started.
edged or non acknowledged.
SADR.
Clock Synchronization
1
2
S
S
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
As soon as a START is detected
SADR
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emp-
tied before the emission/reception of a new character. In this case, to avoid sending/receiving
undesired data, a clock stretching mechanism is implemented.
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition
was not detected. It is tied low until the shift register is loaded.
Figure 32-28 on page 761
DATA0
DATA0
R
Write THR
A
1
DATA0
A
describes the clock synchronization in Read mode.
DATA1
DATA1
CLOCK is tied low by the TWI
as long as THR is empty
A
XXXXXXX
2
DATA2
DATA2
Ack or Nack from the master
NA
S
SAM4S
SAM4S
761
761

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