SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 1041

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
39.7
Table 39-8.
Note:
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
0x98 - 0xAC
0xC4 - 0xE0
0xEC - 0xF8
0x90 - 0x90
Offset
0x0C
0x1C
0x2C
0x3C
0x4C
0x8C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
0x48
0x50
0x54
0x94
0xE4
0xE8
0xFC
Analog-to-Digital Converter (ADC) User Interface
If an offset is not listed in the table it must be considered as “reserved”.
...
Register Mapping
Register
Control Register
Mode Register
Channel Sequence Register 1
Channel Sequence Register 2
Channel Enable Register
Channel Disable Register
Channel Status Register
Reserved
Last Converted Data Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Interrupt Status Register
Reserved
Reserved
Overrun Status Register
Extended Mode Register
Compare Window Register
Channel Gain Register
Channel Offset Register
Channel Data Register 0
Channel Data Register 1
...
Channel Data Register 15
Reserved
Analog Control Register
Reserved
Reserved
Write Protect Mode Register
Write Protect Status Register
Reserved
Reserved
Any offset not listed in
Table 39-8
must be considered as “reserved”.
ADC_SEQR1
ADC_SEQR2
ADC_CDR15
ADC_WPMR
ADC_WPSR
ADC_CHDR
ADC_CHSR
ADC_CHER
ADC_LCDR
ADC_OVER
ADC_CDR0
ADC_CDR1
ADC_CWR
ADC_EMR
ADC_CGR
ADC_COR
ADC_ACR
ADC_IMR
ADC_IER
ADC_IDR
ADC_ISR
ADC_MR
ADC_CR
Name
...
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Access
...
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000100
0x00000000
0x00000000
SAM4S
SAM4S
Reset
...
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