SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 943

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
36.7.16
Name:
Address:
Access:
• WRDY: Write Ready for Synchronous Channels Update
0 = New duty-cycle and dead-time values for the synchronous channels cannot be written.
1 = New duty-cycle and dead-time values for the synchronous channels can be written.
• ENDTX: PDC End of TX Buffer
0 = The Transmit Counter register has not reached 0 since the last write of the PDC.
1 = The Transmit Counter register has reached 0 since the last write of the PDC.
• TXBUFE: PDC TX Buffer Empty
0 = PWM_TCR or PWM_TCNR has a value other than 0.
1 = Both PWM_TCR and PWM_TCNR have a value other than 0.
• UNRE: Synchronous Channels Update Underrun Error
0 = No Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register.
1 = At least one Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register.
• CMPMx: Comparison x Match
0 = The comparison x has not matched since the last read of the PWM_ISR2 register.
1 = The comparison x has matched at least one time since the last read of the PWM_ISR2 register.
• CMPUx: Comparison x Update
0 = The comparison x has not been updated since the last read of the PWM_ISR2 register.
1 = The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.
Note:
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
CMPM7
CMPU7
31
23
15
7
Reading PWM_ISR2 automatically clears flags WRDY, UNRE and CMPSx.
PWM Interrupt Status Register 2
PWM_ISR2
0x40020040
Read-only
CMPU6
CMPM6
30
22
14
6
CMPU5
CMPM5
29
21
13
5
CMPU4
CMPM4
28
20
12
4
CMPM3
CMPU3
UNRE
27
19
11
3
TXBUFE
CMPM2
CMPU2
26
18
10
2
CMPM1
CMPU1
ENDTX
25
17
9
1
SAM4S
SAM4S
CMPM0
CMPU0
WRDY
24
16
8
0
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