SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 243

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
MPU Configuration for a Microcontroller
Ensure the software uses aligned accesses of the correct size to access MPU registers:
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused
regions to prevent any previous region settings from affecting the new MPU setup.
Usually, a microcontroller system has only a single processor and no caches. In such a system,
program the MPU as follows:
Table 11-38. Memory region attributes for a microcontroller
In most microcontroller implementations, the share ability and cache policy attributes do not
affect the system behavior. However, using these settings for the MPU regions can make the
application code more portable. The values given are for typical situations. In special systems,
such as multiprocessor designs or designs with a separate DMA engine, the share ability attri-
bute might be important. In these cases, refer to the recommendations of the memory device
manufacturer.
Memory Region
Flash memory
Internal SRAM
External SRAM
Peripherals
• except for the MPU_RASR register, it must use aligned word accesses
• for the MPU_RASR register, it can use byte or aligned halfword or word accesses.
TEX
b000
b000
b000
b000
C
1
1
1
0
B
0
0
1
1
S
0
1
1
1
Memory Type and Attributes
Normal memory, non-shareable, write-through
Normal memory, shareable, write-through
Normal memory, shareable, write-back, write-allocate
Device memory, shareable
SAM4S
SAM4S
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