SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 198

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.8.2
11.8.2.1
Table 11-28. CMSIS Functions for NVIC Control
198
198
CMSIS Interrupt Control Function
void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
void NVIC_EnableIRQ(IRQn_t IRQn)
void NVIC_DisableIRQ(IRQn_t IRQn)
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
void NVIC_SetPendingIRQ (IRQn_t IRQn)
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
uint32_t NVIC_GetActive (IRQn_t IRQn)
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
uint32_t NVIC_GetPriority (IRQn_t IRQn)
void NVIC_SystemReset (void)
SAM4S
SAM4S
NVIC Design Hints and Tips
NVIC Programming Hints
Ensure that the software uses correctly aligned register accesses. The processor does not sup-
port unaligned accesses to NVIC registers. See the individual register descriptions for the
supported access sizes.
A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents
the processor from taking that interrupt.
Before programming SCB_VTOR to relocate the vector table, ensure that the vector table
entries of the new vector table are set up for fault handlers, NMI and all enabled exception like
interrupts. For more information, see the
The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts.
The CMSIS provides the following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
The input parameter IRQn is the IRQ number. For more information about these functions, see
the CMSIS documentation.
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the
CMSIS:
• the Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to
arrays of 32-bit integers, so that:
– the array ISER[0] to ISER[1] corresponds to the registers ISER0-ISER1
– the array ICER[0] to ICER[1] corresponds to the registers ICER0-ICER1
– the array ISPR[0] to ISPR[1] corresponds to the registers ISPR0-ISPR1
– the array ICPR[0] to ICPR[1] corresponds to the registers ICPR0-ICPR1
– the array IABR[0]to IABR[1] corresponds to the registers IABR0-IABR1
Description
Set the priority grouping
Enable IRQn
Disable IRQn
Return true (IRQ-Number) if IRQn is pending
Set IRQn pending
Clear IRQn pending status
Return the IRQ number of the active interrupt
Set priority for IRQn
Read priority of IRQn
Reset the system
“Vector Table Offset Register”
.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11

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