SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 326

• Manufacturer Part Number: SAM4S16C
• Manufacturer: Atmel Corporation

Specifications of SAM4S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.4.7.3
17.4.7.4
326
326
SAM4S
SAM4S
Clock Alarms
Supply Monitor Detection
The debouncing parameters can be adjusted and are shared (except the wake up input polarity)
by both debouncers. The number of successive identical samples to wake up the core can be
configured from 2 up to 8 in the LPDBC field of SUPC_WUMR. The period of time between 2
samples can be configured by programming the TPERIOD field in the RTC_MR register.
Power parameters can be adjusted by modifying the period of time in the THIGH field in
RTC_MR.
The wake up polarity of the inputs can be independently configured by writing WKUPT0 and
WKUPT1 fields in SUPC_WUMR.
In order to determine which wake up pin triggers the core wake up or simply which debouncer
triggers an event, a status flag is associated for each low power debouncer. These 2 flags can
be read in the SUPC_SR.
A debounce event can perform an immediate clear (0 delay) on half the general purpose backup
registers (GPBR). The LPDBCCLR bit must be set to 1 in SUPC_MR.
The RTC and the RTT alarms can generate a wake up of the core power supply. This can be
enabled by writing respectively, the bits RTCEN and RTTEN to 1 in the Supply Controller Wake
Up Mode Register (SUPC_WUMR).
The Supply Controller does not provide any status as the information is available in the User
Interface of either the Real Time Timer or the Real Time Clock.
The supply monitor can generate a wakeup of the core power supply. See
ply
Monitor”.
Section 17.4.4 ”Sup-
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11