SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 104

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.4.8
104
104
SAM4S
SAM4S
LDREX and STREX
Load and Store Register Exclusive.
Syntax
where:
cond
Rd
Rt
Rn
offset
Operation
LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory
address.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a
memory address. The address used in any Store-Exclusive instruction must be the same as the
address in the most recently executed Load-exclusive instruction. The value stored by the Store-
Exclusive instruction must also have the same data size as the value loaded by the preceding
Load-exclusive instruction. This means software must always use a Load-exclusive instruction
and a matching Store-Exclusive instruction to perform a synchronization operation, see
chronization Primitives”
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does
not perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction
writes 0 to the destination register, it is guaranteed that no other process in the system has
accessed the memory location between the Load-exclusive and Store-Exclusive instructions.
For reasons of performance, keep the number of instructions between corresponding Load-
Exclusive and Store-Exclusive instruction to a minimum.
The result of executing a Store-Exclusive instruction to an address that is different from that
used in the preceding Load-Exclusive instruction is unpredictable.
Restrictions
In these instructions:
• do not use PC
• do not use SP for Rd and Rt
• for STREX, Rd must be different from both Rt and Rn
• the value of offset must be a multiple of four in the range 0-1020.
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
is an optional condition code, see
is the destination register for the returned status.
is the register to load or store.
is the register on which the memory address is based.
is an optional offset applied to the value in Rn.
If offset is omitted, the address is the value in Rn.
.
“Conditional Execution”
.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
“Syn-

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