SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 246

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.11.2.2
Name:
Access:
Reset:
The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of
the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers.
• PRIVDEFENA: Privileged Default Memory Map Enabled
Enables privileged software access to the default memory map:
0: If the MPU is enabled, disables the use of the default memory map. Any memory access to a location not covered by any
enabled region causes a fault.
1: If the MPU is enabled, enables the use of the default memory map as a background region for privileged software
accesses.
When enabled, the background region acts as a region number -1. Any region that is defined and enabled has priority over
this default map.
If the MPU is disabled, the processor ignores this bit.
• HFNMIENA: Hard Fault and NMI Enabled
Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit.
1: the MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1, the behavior is unpredictable.
• ENABLE
Enables the MPU:
0: MPU disabled.
1: MPU enabled.
When ENABLE and PRIVDEFENA are both set to 1:
246
246
• For privileged accesses, the default memory map is as described in
software that does not address an enabled memory region behaves as defined by the default memory map.
23
15
31
7
SAM4S
SAM4S
MPU Control Register
MPU_CTRL
Read-write
0x00000800
22
14
30
6
21
13
29
5
20
12
28
4
19
11
27
3
“Memory Model”
PRIVDEFENA
26
18
10
2
. Any access by privileged
HFNMIENA
25
17
9
1
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
ENABLE
24
16
8
0

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