SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 1068

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
40.6.4
40.6.5
40.6.6
1068
1068
SAM4S
SAM4S
Conversion FIFO
Channel Selection
Sleep Mode
A 4 half-word FIFO is used to handle the data to be converted.
As long as the TXRDY flag in the
ready to accept conversion requests by writing data into
which cannot be converted immediately are stored in the DACC FIFO.
When the FIFO is full or the DACC is not ready to accept conversion requests, the TXRDY flag
is inactive.
The WORD field of the
word transfer for writing into the FIFO.
In half-word transfer mode only the 16 LSB of DACC_CDR data are taken into account,
DACC_CDR[15:0] is stored into the FIFO.
DACC_CDR[11:0] field is used as data and the DACC_CDR[15:12] bits are used for channel
selection if the TAG field is set in DACC_MR register.
In word transfer mode each time the DACC_CDR register is written 2 data items are stored in
the FIFO. The first data item sampled for conversion is DACC_CDR[15:0] and the second
DACC_CDR[31:16].
Fields DACC_CDR[15:12] and DACC_CDR[31:28] are used for channel selection if the TAG
field is set in DACC_MR register.
Warning: Writing in the DACC_CDR register while TXRDY flag is inactive will corrupt FIFO
data.
There are two means by which to select the channel to perform data conversion.
The DACC Sleep Mode maximizes power saving by automatically deactivating the DACC when
it is not being used for conversions.
When a start conversion request occurs, the DACC is automatically activated. As the analog cell
requires a start-up time, the logic waits during this time and starts the conversion on the selected
channel. When all conversion requests are complete, the DACC is deactivated until the next
request for conversion.
A fast wake-up mode is available in the
saving strategy and responsiveness. Setting the FASTW bit to 1 enables the fast wake-up
mode. In fast wake-up mode the DACC is not fully deactivated while no conversion is requested,
thereby providing less power saving but faster wake-up (4 times faster).
• By default, to select the channel where to convert the data, is to use the USER_SEL field of
• A more flexible option to select the channel for the data to be converted to is to use the tag
the
with the USER_SEL field.
mode, setting the TAG field of the
DACC_CDR[13:12] which are otherwise unused, are employed to select the channel in the
same way as with the USER_SEL field. Finally, if the WORD field is set, the 2 bits,
DACC_CDR[13:12] are used for channel selection of the first data and the 2 bits,
DACC_CDR[29:28] for channel selection of the second data.
DACC Mode
Register. Data requests will merely be converted to the channel selected
DACC Mode Register
DACC Interrupt Status Register
DACC Mode Register
DACC Mode Register
allows the user to switch between half-word and
DACC Conversion Data
to 1. In this mode the 2 bits,
as a compromise between power
is active the DAC Controller is
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Register. Data

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