SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 324

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
17.4.6.2
17.4.7
Figure 17-4. Wake Up Sources
17.4.7.1
324
324
WKUP15
WKUP0
WKUP1
SAM4S
SAM4S
Wake Up Sources
Brownout Detector Reset
Wake Up Inputs
rtc_alarm
rtt_alarm
sm_out
Falling/Rising
Falling/Rising
Falling/Rising
WKUPT15
WKUPT0
WKUPT1
Detector
Detector
Detector
Edge
Edge
Edge
The brownout detector provides the bodcore_in signal to the SUPC which indicates that the volt-
age regulation is operating as programmed. If this signal is lost for longer than 1 slow clock
period while the voltage regulator is enabled, the Supply Controller can assert vddcore_nreset.
This feature is enabled by writing the bit, BODRSTEN (Brownout Detector Reset Enable) to 1 in
the Supply Controller Mode Register (SUPC_MR).
If BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low),
the vddcore_nreset signal is asserted for a minimum of 1 slow clock cycle and then released if
bodcore_in has been reactivated. The BODRSTS bit is set in the Supply Controller Status Reg-
ister (SUPC_SR) so that the user can know the source of the last reset.
Until bodcore_in is deactivated, the vddcore_nreset signal remains active.
The wake up events allow the device to exit backup mode. When a wake up event is detected,
the Supply Controller performs a sequence which automatically reenables the core power
supply.
The wake up inputs, WKUP0 to WKUP15, can be programmed to perform a wake up of the core
power supply. Each input can be enabled by writing to 1 the corresponding bit, WKUPEN0 to
WKUPEN 15, in the Wake Up Inputs Register (SUPC_WUIR). The wake up level can be
selected with the corresponding polarity bit, WKUPPL0 to WKUPPL15, also located in
SUPC_WUIR.
All the resulting signals are wired-ORed to trigger a debounce counter, which can be pro-
grammed with the WKUPDBC field in the Supply Controller Wake Up Mode Register
(SUPC_WUMR). The WKUPDBC field can select a debouncing period of 3, 32, 512, 4,096 or
RTCEN
RTTEN
SMEN
WKUPEN15
WKUPEN0
WKUPEN1
WKUPIS0
WKUPIS15
WKUPIS1
SLCK
WKUPDBC
Debouncer
WKUPS
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Core
Supply
Restart

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