SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 219

no-image

SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.9.1.7
Name:
Access:
Reset:
The SCB_CCR register controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults esca-
lated by FAULTMASK to ignore BusFaults. It also enables the division by zero and unaligned access trapping, and the
access to the NVIC_STIR register by unprivileged software (see
• STKALIGN: Stack Alignment
Indicates the stack alignment on exception entry:
0: 4-byte aligned.
1: 8-byte aligned.
On exception entry, the processor uses bit [9] of the stacked PSR to indicate the stack alignment. On return from the
exception, it uses this stacked bit to restore the correct stack alignment.
• BFHFNMIGN: Bus Faults Ignored
Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the
hard fault and FAULTMASK escalated handlers:
0: data bus faults caused by load and store instructions cause a lock-up.
1: handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe sys-
tem devices and bridges to detect control path problems and fix them.
• DIV_0_TRP: Division by Zero Trap
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:
0: do not trap divide by 0.
1: trap divide by 0.
When this bit is set to 0, a divide by zero returns a quotient of 0.
• UNALIGN_TRP: Unaligned Access Trap
Enables unaligned access traps:
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
31
23
15
7
Configuration and Control Register
SCB_CCR
Read-write
0x000000000
30
22
14
6
29
21
13
5
DIV_0_TRP
28
20
12
4
UNALIGN_TRP
“Software Trigger Interrupt Register”
27
19
11
3
26
18
10
2
USERSETMPE
STKALIGN
ND
25
17
9
1
).
NONBASETHR
SAM4S
SAM4S
BFHFNMIGN
DENA
24
16
8
0
219
219

Related parts for SAM4S16C