SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 823

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Figure 34-20. 2-bit Gray Up/Down Counter.
34.6.16
34.6.17
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
TIOAx
TIOBx
DOWNx
Write Protection System
Fault Mode
TC_RCx
In order to bring security to the Timer Counter, a write protection system has been implemented.
The write protection mode prevent the write of TC_BMR, TC_FMR, TC_CMRx, TC_SMMRx,
TC_RAx, TC_RBx, TC_RCx registers. When this mode is enabled and one of the protected reg-
isters write, the register write request canceled.
Due to the nature of the write protection feature, enabling and disabling the write protection
mode requires the use of a security code. Thus when enabling or disabling the write protection
mode the WPKEY field of the TC_WPMR register must be filled with the “TIM” ASCII code (cor-
responding to 0x54494D) otherwise the register write will be canceled.
At anytime, the TC_RCx registers can be used to perform a comparison on the respective cur-
rent channel counter value (TC_CVx) with the value of TC_RCx register.
The CPCSx flags can be set accordingly and an interrupt can be generated.
This interrupt is processed but requires an unpredictable amount of time to be achieve the
required action.
It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 register
and/or CPCS from TC_SR1 register. Each source can be independently enabled/disabled by
means of TC_FMR register.
This can be useful to detect an overflow on speed and/or position when QDEC is processed and
to act immediately by using the FAULT output.
Figure 34-21. Fault Output Generation
TC_SR0 flag CPCS
TC_SR1 flag CPCS
TC_FMR / ENCF0
TC_FMR / ENCF1
WAVEx = GCENx =1
AND
AND
OR
FAULT (to PWM input)
SAM4S
SAM4S
823
823

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