SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 895

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
36. Pulse Width Modulation (PWM) Controller
36.1
36.2
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Description
Embedded Characteristics
The PWM macrocell controls 4 channels independently. Each channel controls two complemen-
tary square output waveforms. Characteristics of the output waveforms such as period, duty-
cycle, polarity and dead-times (also called dead-bands or non-overlapping times) are configured
through the user interface. Each channel selects and uses one of the clocks provided by the
clock generator. The clock generator provides several clocks resulting from the division of the
PWM master clock (MCK).
All PWM macrocell accesses are made through registers mapped on the peripheral bus. All
channels integrate a double buffering system in order to prevent an unexpected output wave-
form while modifying the period, the duty-cycle or the dead-times.
Channels can be linked together as synchronous channels to be able to update their duty-cycle
or dead-times at the same time.
The update of duty-cycles of synchronous channels can be performed by the Peripheral DMA
Controller Channel (PDC) which offers buffer transfer without processor Intervention.
The PWM macrocell provides 8 independent comparison units capable of comparing a pro-
grammed value to the counter of the synchronous channels (counter of channel 0). These
comparisons are intended to generate software interrupts, to trigger pulses on the 2 indepen-
dent event lines (in order to synchronize ADC conversions with a lot of flexibility independently of
the PWM outputs), and to trigger PDC transfer requests.
The PWM outputs can be overridden synchronously or asynchronously to their channel counter.
The PWM block provides a fault protection mechanism with 6 fault inputs
fault condition and to override the PWM outputs asynchronously.
For safety usage, some control registers are write-protected.
• Four-channel 16-bit PWM Controller
• Common clock generator, providing thirteen different clocks
• Independent Channels
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– Independent 16-bit counter for each channel
– Independent complementary outputs with W-bit dead-time generator (also called
– Independent enable disable command for each channel
– Independent clock selection for each channel
– Independent Period, duty-cycle and dead-time for each channel
– Independent double buffering of period, duty-cycle and dead-times for each channel
– Independent programmable selection of the output waveform polarity for each
– Independent programmable center or left aligned output waveform for each channel
dead-band or non-overlapping time) for each channel
channel
, cap
able of detecting a
SAM4S
SAM4S
895
895

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