SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 646

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
30.7.3.9
646
646
SAM4S
SAM4S
Peripheral Deselection with PDC
lines to remain in their current state (low = active) until transfer to another chip select is required.
Even if the SPI_TDR is not reloaded the chip select will remain active. To have the chip select
line to raise at the end of the transfer the Last transfer Bit (LASTXFER) in the SPI_MR register
must be set at 1 before writing the last data to transmit into the SPI_TDR.
When the Peripheral DMA Controller is used, the chip select line will remain low during the
whole transfer since the TDRE flag is managed by the PDC itself. The reloading of the SPI_TDR
by the PDC is done as soon as TDRE flag is set to one. In this case the use of CSAAT bit might
not be needed. However, it may happen that when other PDC channels connected to other
peripherals are in use as well, the SPI PDC might be delayed by another (PDC with a higher pri-
ority on the bus). Having PDC buffers in slower memories like flash memory or SDRAM
compared to fast internal SRAM, may lengthen the reload time of the SPI_TDR by the PDC as
well. This means that the SPI_TDR might not be reloaded in time to keep the chip select line
low. In this case the chip select line may toggle between data transfer and according to some
SPI Slave devices, the communication might get lost. The use of the CSAAT bit might be
needed.
When the CSAAT bit is set at 0, the NPCS does not rise in all cases between two transfers on
the same peripheral. During a transfer on a Chip Select, the flag TDRE rises as soon as the con-
tent of the SPI_TDR is transferred into the internal shifter. When this flag is detected the
SPI_TDR can be reloaded. If this reload occurs before the end of the current transfer and if the
next transfer is performed on the same chip select as the current transfer, the Chip Select is not
de-asserted between the two transfers. This might lead to difficulties for interfacing with some
serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate
interfacing with such devices, the Chip Select Register can be programmed with the CSNAAT bit
(Chip Select Not Active After Transfer) at 1. This allows to de-assert systematically the chip
select lines during a time DLYBCS. (The value of the CSNAAT bit is taken into account only if
the CSAAT bit is set at 0 for the same Chip Select).
Figure 30-11
CSNAAT bits.
shows different peripheral deselection cases and the effect of the CSAAT and
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11

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