SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 71

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Figure 11-6. Exception Stack Frame
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
The alignment of the stack frame is controlled via the STKALIGN bit of the Configuration Control
Register (CCR).
The stack frame includes the return address. This is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the excep-
tion handler start address from the vector table. When stacking is complete, the processor starts
executing the exception handler. At the same time, the processor writes an EXC_RETURN
value to the LR. This indicates which stack pointer corresponds to the stack frame and what
operation mode the processor was in before the entry occurred.
If no higher priority exception occurs during the exception entry, the processor starts executing
the exception handler and automatically changes the status of the corresponding pending inter-
rupt to active.
If another higher priority exception occurs during the exception entry, the processor starts exe-
cuting the exception handler for this exception and does not change the pending status of the
earlier exception. This is the late arrival case.
floating-point storage
Exception frame with
{aligner}
FPSCR
S15
S14
S13
S12
S11
S10
xPSR
S9
S8
S7
S6
S5
S4
R12
S2
S1
PC
S3
S0
LR
R3
R2
R1
R0
...
Decreasing
address
memory
Pre-IRQ top of stack
IRQ top of stack
Exception frame without
floating-point storage
{aligner}
xPSR
PC
R12
LR
R0
R3
R2
R1
...
Pre-IRQ top of stack
IRQ top of stack
SAM4S
SAM4S
71
71

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