SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 772

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
32.11.6
Name:
Address:
Access:
Reset:
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in
page 763
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in
RXRDY behavior in Slave mode can be seen in
page 763
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in
772
772
TXBUFE
31
23
15
7
SAM4S
SAM4S
and
and
TWI Status Register
TWI_SR
0x40018020 (0), 0x4001C020 (1)
Read-only
0x0000F009
Figure 32-31 on page
Figure 32-31 on page
RXBUFF
OVRE
30
22
14
6
ENDTX
GACC
763.
763.
29
21
13
5
Figure 32-8 on page
Figure 32-10 on page
Figure 32-26 on page
ENDRX
SVACC
Figure 32-28 on page
Figure 32-8 on page 744
28
20
12
4
EOSACC
SVREAD
27
19
11
3
744.
745.
759,
761,
and in
Figure 32-29 on page
Figure 32-29 on page
SCLWS
TXRDY
26
18
10
Figure 32-10 on page
2
ARBLST
RXRDY
25
17
9
1
762,
762,
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
745.
Figure 32-30 on
Figure 32-30 on
TXCOMP
NACK
24
16
8
0

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