SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 1039

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
39.6.10
39.6.11
39.6.12
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
ADC Timings
Automatic Calibration
Buffer Structure
Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in
the Mode Register, ADC_MR.
A minimal Tracking Time is necessary for the ADC to guarantee the best converted final value
between two channel selections. This time has to be programmed through the TRACKTIM bit
field in the Mode Register, ADC_MR.
When the gain, offset or differential input parameters of the analog cell change between two
channels, the analog cell may need a specific settling time before starting the tracking phase. In
that case, the controller automatically waits during the settling time defined in the
Register”. Obviously, if the ANACH option is not set, this time is unused.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be
taken into consideration to program a precise value in the TRACKTIM field. See the product
ADC Characteristics section.
The ADC features an automatic calibration (AUTOCALIB) mode for offset and gain errors
(calibration).
The automatic calibration sequence can be started at any time writing to '1' the AUTOCAL bit of
the ADC Control Register. The end of calibration sequence is given by the EOCAL bit in the
interrupt status register (ADC_ISR), and an interrupt is generated if EOCAL interrupt has been
enabled (ADC_IER).
The calibration sequence will perform an automatic calibration on all enabled channels. The gain
and offset settings of all enabled channels must be set before starting the AUTOCALIB
sequence. If the gain and offset settings (ADC_CGR and ADC_COR registers) for a given chan-
nel are changed, the AUTOCALIB sequence must then be started again.
The calibration data (on one or more enabled channels) is stored in the internal ADC memory.
Then, when a new conversion is started (on one or more enabled channels), the converted
value (in ADC_LCDR or ADC_CDRx registers) is a calibrated value.
Autocalibration is for settings, not for channels. Therefore, if a specific combination of gain and
offset has been already calibrated, and a new channel with the same settings is enabled after
the initial calibration, there is no need to restart a calibration. If different enabled channels have
different gain and offset settings, the corresponding channels must be enabled before starting
the calibration.
If a software reset is performed (SWRST bit in ADC_CR) or after power up (or wake-up from
Backup mode), the calibration data in the ADC memory is lost.
Changing the ADC running mode (in ADC_CR register) does not affect the calibration data.
Changing the ADC reference voltage (ADVREF pin) requires a new calibration sequence.
For calibration time, offset and gain error after calibration, refer to the 12-bit ADC electrical char-
acteristics section of the product.
The PDC read channel is triggered each time a new data is stored in ADC_LCDR register. The
same structure of data is repeatedly stored in ADC_LCDR register each time a trigger event
occurs. Depending on user mode of operation (ADC_MR, ADC_CHSR, ADC_SEQR1,
SAM4S
SAM4S
“ADC Mode
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