SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 210

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.9.1.1
Name:
Access:
Reset:
The SCB_ACTLR register provides disable bits for the following processor functions:
By default, this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally
require modification.
• DISOOFP: Disable Out Of Order Floating Point
Disables floating point instructions that complete out of order with respect to integer instructions.
• DISFPCA: Disable FPCA
Disables an automatic update of CONTROL.FPCA.
• DISFOLD: Disable Folding
When set to 1, disables the IT folding.
Note:
• DISDEFWBUF: Disable Default Write Buffer
When set to 1, it disables the write buffer use during default memory map accesses. This causes BusFault to be precise
but decreases the performance, as any store to memory must complete before the processor can execute the next
instruction.
This bit only affects write buffers implemented in the Cortex-M4 processor.
• DISMCYCINT: Disable Multiple Cycle Interruption
When set to 1, it disables the interruption of load multiple and store multiple instructions. This increases the interrupt
latency of the processor, as any LDM or STM must complete before the processor can stack the current state and enter the
interrupt handler.
210
210
• IT folding
• write buffer use for accesses to the default memory map
• interruption of multi-cycle instructions.
31
23
15
7
In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT instruction.
This behavior is called IT folding, and it improves the performance. However, IT folding can cause jitter in looping. If a task must
avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable the IT folding.
SAM4S
SAM4S
Auxiliary Control Register
SCB_ACTLR
Read-write
0x000000000
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
DISFOLD
26
18
10
2
DISDEFWBUF
DISOOFP
25
17
9
1
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
DISMCYCINT
DISFPCA
24
16
8
0

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