SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 55

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.4.1.17
11.4.1.18
11.4.1.19
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Exceptions and Interrupts
Data Types
Cortex Microcontroller Software Interface Standard (CMSIS)
The Cortex-M4 processor supports interrupts and system exceptions. The processor and the
Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception
changes the normal flow of software control. The processor uses the Handler mode to handle all
exceptions except for reset. See
information.
The NVIC registers control interrupt handling. See
for more information.
The processor supports the following data types:
For a Cortex-M4 microcontroller system, the Cortex Microcontroller Software Interface Standard
(CMSIS) defines:
The CMSIS includes address definitions and data structures for the core peripherals in the Cor-
tex-M4 processor.
The CMSIS simplifies the software development by enabling the reuse of template code and the
combination of CMSIS-compliant software components from various middleware vendors. Soft-
ware vendors can expand the CMSIS to include their peripheral definitions and access functions
for those peripherals.
This document includes the register names defined by the CMSIS, and gives short descriptions
of the CMSIS functions that address the processor core and the core peripherals.
Note:
The following sections give more information about the CMSIS:
• 32-bit words
• 16-bit halfwords
• 8-bit bytes
• The processor manages all data memory accesses as little-endian. Instruction memory and
• a common way to:
• the names of:
• a device-independent interface for RTOS kernels, including a debug channel.
Private Peripheral Bus (PPB) accesses are always little-endian. See
Types and Attributes”
Section 11.5.3 ”Power Management Programming Hints”
Section 11.6.2 ”CMSIS Functions”
Section 11.8.2.1 ”NVIC Programming Hints”
– access peripheral registers
– define exception vectors
– the registers of the core peripherals
– the core exception vectors
This document uses the register short names defined by the CMSIS. In a few cases, these differ
from the architectural short names that might be used in other documents.
for more information.
“Exception Entry”
.
“Nested Vectored Interrupt Controller (NVIC)”
and
“Exception Return”
“Memory Regions,
SAM4S
SAM4S
for more
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