SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 342

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Figure 19-3. Code Read Optimization for FWS = 3
Note:
19.4.2.3
Figure 19-4. Data Read Optimization for FWS = 1
342
342
Buffer (128bits)
Buffer 1 (128bits)
Buffer 0 (128bits)
ARM Request
Data To ARM
Flash Access
Master Clock
ARM Request
Data To ARM
Flash Access
Master Clock
When FWS is included between 1 and 3, in case of sequential reads, the first access takes (FWS+1) cycles, the other ones only
1 cycle.
(32-bit)
SAM4S
SAM4S
(32-bit)
Data Read Optimization
@Byte 0
XXX
@Byte 0
XXX
XXX
The organization of the Flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit)
prefetch buffers and one 128-bit (or 64-bit) data read buffer, thus providing maximum system
performance. This buffer is added in order to store the requested data plus all the data contained
in the 128-bit (64-bit) aligned data. This speeds up sequential data reads if, for example, FWS is
equal to 1 (see
Note:
Bytes 0-15
XXX
XXX
Bytes 0-15
Bytes 0-3
@ 4
No consecutive data read accesses are mandatory to benefit from this optimization.
XXX
@ 8
4-7
Figure
@4
0-3
19-4).
@ 12
@8
8-11
4-7
Bytes 0-15
@12 @16
Bytes 16-31
8-11
12-15
@ 16
12-15
Bytes 0-15
@20
Bytes 16-31
16-19 20-23
@24
@ 20
16-19
@28 @32
Bytes 32-47
24-27
@ 24
20-23
28-31 32-35
24-27
@ 28
@36 @40
Bytes 16-31
Bytes 16-31
36-39
28-31
@ 32
@44 @48 @52
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Bytes 48-63
Bytes 32-47
40-43
Bytes 32-47
44-47
@ 36
32-35
48-51

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