SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 111

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.5.3
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with
Extend.
Syntax
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op
S
Rd
Rm
Rs
n
MOVS Rd, Rm
Operation
ASR
specified by constant
RRX
In all these instructions, the result is written to
unchanged. For details on what result is generated by the different instructions, see
ations”
Restrictions
Do not use SP and do not use PC.
Condition Flags
If
Examples
• these instructions update the N and Z flags according to the result
• the C flag is updated to the last bit shifted out, except when the shift length is 0, see
S
Operations”
,
is specified:
moves the bits in register
LSL
.
,
LSR
is the preferred syntax for
, and
.
is one of:
ASR
LSL
LSR
ROR
is an optional suffix. If
of the operation, see
is the destination register.
is the register holding the value to be shifted.
is the register holding the shift length to apply to the value in
significant byte is used and can be in the range 0 to 255.
is the shift length. The range of shift length depends on the instruction:
ASR
LSL
LSR
ROR
ROR
Logical Shift Left.
shift length from 0 to 31
Logical Shift Right.
shift length from 1 to 32
Arithmetic Shift Right.
shift length from 1 to 32
Rotate Right.
shift length from 1 to 31.
n
move the bits in the register
or register
Rm
to the right by 1.
Rs
“Conditional Execution”
S
.
is specified, the condition code flags are updated on the result
LSLS Rd, Rm, #0
.
Rm
Rd
to the left or right by the number of places
, but the value in register
.
Rm
. Only the least
SAM4S
SAM4S
Rm
“Shift Oper-
remains
“Shift
111
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