SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 181

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.10.4
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
TBB and TBH
Table Branch Byte and Table Branch Halfword.
Syntax
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
where:
Rn
Rm
Operation
These instructions cause a PC-relative forward branch using a table of single byte offsets for
TBB
the table. For
table. and for
table. The branch occurs to the address at that offset from the address of the byte immediately
after the
Restrictions
The restrictions are:
Condition Flags
These instructions do not change the flags.
Examples
Case1
; an instruction sequence follows
Case2
; an instruction sequence follows
Case3
; an instruction sequence follows
BranchTable_Byte
• when any of these instructions is used inside an IT block, it must be the last instruction of the
ADR.W R0, BranchTable_Byte
TBB [R0, R1]
DCB
DCB
DCB
TBH
, or halfword offsets for
Rn
Rm
IT block.
must not be SP
must not be SP and must not be PC
TBB
[PC, R1, LSL #1] ; R1 is the index, PC is used as base of the
0
((Case2-Case1)/2) ; Case2 offset calculation
((Case3-Case1)/2) ; Case3 offset calculation
or
TBH
TBB
is the register containing the address of the table of branch lengths.
If
following the
is the index register. This contains an index into the table. For halfword tables,
doubles the value in
TBH
Rn
the branch offset is twice the unsigned value of the halfword returned from the
the branch offset is twice the unsigned value of the byte returned from the
instruction.
is PC, then the address of the table is the address of the byte immediately
; branch table
; R1 is the index, R0 is the base address of the
TBB
TBH
; branch table
; Case1 offset calculation
.
or
Rn
TBH
Rm
provides a pointer to the table, and
instruction.
to form the right offset into the table.
Rm
supplies an index into
SAM4S
SAM4S
LSL #1
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