SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 254

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Halfword
Illegal instruction
Implementation-defined
Implementation-specific
Index register
Instruction cycle count
Interrupt handler
Interrupt vector
Little-endian (LE)
Little-endian memory
Load/store architecture
Memory Protection Unit
(MPU)
Prefetching
SAM4S
SAM4S
An instruction that is architecturally Undefined.
A 16-bit data item.
The behavior is not architecturally defined, but is defined and documented by individual
implementations.
The behavior is not architecturally defined, and does not have to be documented by individual
implementations. Used when there are a number of implementation options available and the option
chosen does not affect software compatibility.
In some load and store instruction descriptions, the value of this register is used as an offset to be
added to or subtracted from the base register value to form the address that is sent to memory. Some
addressing modes optionally enable the index register value to be shifted prior to the addition or
subtraction.
See also
The number of cycles that an instruction occupies the Execute stage of the pipeline.
A program that control of the processor is passed to when an interrupt occurs.
One of a number of fixed addresses in low memory, or in high memory if high vectors are configured,
that contains the first instruction of the corresponding interrupt handler.
Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing
addresses in memory.
See also
Memory in which:
a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at
that address,
a byte at a halfword-aligned address is the least significant byte within the halfword at that address.
See also
A processor architecture where data-processing operations only operate on register contents, not
directly on memory contents.
Hardware that controls access permissions to blocks of memory. An MPU does not perform any
address translation.
In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before
the preceding instructions have finished executing. Prefetching an instruction does not mean that the
instruction has to be executed.
“Base register”
“Big-endian (BE)”
“Big-endian memory”
.
,
“Byte-invariant”
.
,
“Endianness”
.
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11

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