SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 645

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Figure 30-10. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation
30.7.3.8
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
SPI Master
Peripheral Deselection without PDC
NPCS0
NPCS1
NPCS2
NPCS3
SPCK
MISO
MOSI
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated,
each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0
defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the
PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on
the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
an implementation.
If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must
be disabled. This is not needed for all other chip select lines since Mode Fault Detection is only
on NPCS0.
During a transfer of more than one data on a Chip Select without the PDC, the SPI_TDR is
loaded by the processor, the flag TDRE rises as soon as the content of the SPI_TDR is trans-
ferred into the internal shift register. When this flag is detected high, the SPI_TDR can be
reloaded. If this reload by the processor occurs before the end of the current transfer and if the
next transfer is performed on the same chip select as the current transfer, the Chip Select is not
de-asserted between the two transfers. But depending on the application software handling the
SPI status register flags (by interrupt or polling method) or servicing other interrupts or other
tasks, the processor may not reload the SPI_TDR in time to keep the chip select active (low). A
null Delay Between Consecutive Transfer (DLYBCT) value in the SPI_CSR register, will give
even less time for the processor to reload the SPI_TDR. With some SPI slave peripherals,
requiring the chip select line to remain active (low) during a full set of transfers might lead to
communication errors.
To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be pro-
grammed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select
1-of-n Decoder/Demultiplexer
SPCK
Slave 0
MISO MOSI
NSS
SPCK MISO MOSI
Slave 1
NSS
Figure 30-10
SPCK MISO MOSI
below shows such
Slave 14
NSS
SAM4S
SAM4S
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