SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 936

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
36.7.9
Name:
Address:
Access:
This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in
page
• SYNCx: Synchronous Channel x
0 = Channel x is not a synchronous channel.
1 = Channel x is a synchronous channel.
• UPDM: Synchronous Channels Update Mode
Notes:
• PTRM: PDC Transfer Request Mode
• PTRCS: PDC Transfer Request Comparison Selection
Selection of the comparison used to set the flag WRDY and the corresponding PDC transfer request.
936
936
Value
UPDM
0
1
2
3
0
1
2
959.
31
23
15
7
1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in
2. The update occurs when the Update Period is elapsed.
SAM4S
SAM4S
PWM Sync Channels Mode Register
MODE0
MODE1
MODE2
Control Register”
Name
PTRM
PWM_SCM
0x40020020
Read-write
x
x
0
1
PTRCS
30
22
14
6
Manual write of double buffer registers and manual update of synchronous channels
Manual write of double buffer registers and automatic update of synchronous channels
Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels
Reserved
The WRDY flag in
1.
The WRDY flag in
elapsed, the PDC transfer request is never set to 1.
The WRDY flag in
as soon as the update period is elapsed.
The WRDY flag in
as soon as the selected comparison matches.
WRDY Flag and PDC Transfer Request
is set.
29
21
13
5
“PWM Interrupt Status Register 2” on page 943
“PWM Interrupt Status Register 2” on page 943
“PWM Interrupt Status Register 2” on page 943
“PWM Interrupt Status Register 2” on page 943
PTRM
28
20
12
4
SYNC3
Description
27
19
11
3
SYNC2
and the PDC transfer request are never set to
“PWM Write Protect Status Register” on
is set to 1 as soon as the update period is
and the PDC transfer request are set to 1
and the PDC transfer request are set to 1
26
18
10
2
“PWM Sync Channels Update
SYNC1
25
17
(1)
9
1
(2)
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
UPDM
SYNC0
24
16
8
0
(2)

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