SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 1069

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
40.6.7
Figure 40-2. Conversion Sequence
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Write DACC_CDR
Selected Channel
Write USER_SEL
Read DACC_ISR
DAC Channel 0
DAC Channel 1
Output
Output
field
TXRDY
MCK
EOC
DACC Timings
None
Select Channel 0
The DACC startup time must be defined by the user in the STARTUP field of the
Register.
This startup time differs depending of the use of the fast wake-up mode along with sleep mode,
in this case the user must set the STARTUP time corresponding to the fast wake up and not the
standard startup time.
A max speed mode is available by setting the MAXS bit to 1 in the DACC_MR register. Using
this mode, the DAC Controller no longer waits to sample the end of cycle signal coming from the
DACC block to start the next conversion and uses an internal counter instead. This mode gains
2 DACC Clock periods between each consecutive conversion.
Warning: Using this mode, the EOC interrupt of the DACC_IER register should not be used as it
is 2 DACC Clock periods late.
After 20 µs the analog voltage resulting from the converted data will start decreasing, therefore it
is necessary to refresh the channel on a regular basis to prevent this voltage loss. This is the
purpose of the REFRESH field in the DACC Mode Register where the user will define the period
for the analog channels to be refreshed.
Warning: A REFRESH PERIOD field set to 0 will disable the refresh function of the DACC
channels.
Data 0 Data 1
Channel 0
Data 0
Select Channel 1
Data 2
CDR FIFO not full
Data 1
Channel 1
SAM4S
SAM4S
DACC Mode
Data 2
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