SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 63

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.4.2.8
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Programming Hints for the Synchronization Primitives
To perform an exclusive read-modify-write of a memory location, the software must:
The software can use the synchronization primitives to implement a semaphore as follows:
The Cortex-M4 includes an exclusive access monitor, that tags the fact that the processor has
executed a Load-Exclusive instruction. If the processor is part of a multiprocessor system, the
system also globally tags the memory locations addressed by exclusive accesses by each
processor.
The processor removes its exclusive access tag if:
In a multiprocessor implementation:
For more information about the synchronization primitive instructions, see
”LDREX and STREX”
ISO/IEC C cannot directly generate the exclusive access instructions. CMSIS provides intrinsic
functions for generation of these instructions:
Table 11-8.
Instruction
LDREX
LDREXH
LDREXB
1. Use a Load-Exclusive instruction to read the value of the location.
2. Update the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory
4. Test the returned status bit. If this bit is:
1. Use a Load-Exclusive instruction to read from the semaphore address to check
2. If the semaphore is free, use a Store-Exclusive instruction to write the claim value to the
3. If the returned status bit from step 2 indicates that the Store-Exclusive instruction suc-
• It executes a CLREX instruction
• It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
• An exception occurs. This means that the processor can resolve semaphore conflicts
• Executing a CLREX instruction removes only the local exclusive access tag for the processor
• executing a Store-Exclusive instruction, or an exception, removes the local exclusive access
between different threads.
tags, and all global exclusive access tags for the processor.
0: The read-modify-write completed successfully.
1: No write was performed. This indicates that the value returned at step 1 might be out of
date. The software must retry the read-modify-write sequence.
location
whether the semaphore is free.
semaphore address.
ceeded then the software has claimed the semaphore. However, if the Store-Exclusive
instruction failed, another process might have claimed the semaphore after the soft-
ware performed the first step.
CMSIS Functions for Exclusive Access Instructions
and
uint32_t __LDREXW (uint32_t *addr)
uint16_t __LDREXH (uint16_t *addr)
uint8_t __LDREXB (uint8_t *addr)
CMSIS Function
Section 11.6.4.9 ”CLREX”
.
Section 11.6.4.8
SAM4S
SAM4S
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