SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 88

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
11.6.3.6
11.6.3.7
88
88
Condition Flags
SAM4S
SAM4S
PC-relative Expressions
Conditional Execution
the UNALIGN_TRP bit in the Configuration and Control Register to trap all unaligned accesses,
see
A PC-relative expression or label is a symbol that represents the address of an instruction or lit-
eral data. It is represented in the instruction as the PC value plus or minus a numeric offset. The
assembler calculates the required offset from the label and the address of the current instruc-
tion. If the offset is too big, the assembler produces an error.
Most data processing instructions can optionally update the condition flags in the Application
Program Status Register (APSR) according to the result of the operation, see
gram Status Register”
flag is not updated, the original value is preserved. See the instruction descriptions for the flags
they affect.
An instruction can be executed conditionally, based on the condition flags set in another instruc-
tion, either:
Conditional execution is available by using conditional branches or by adding condition code
suffixes to instructions. See
them conditional instructions. The condition code suffix enables the processor to test a condition
based on the flags. If the condition test of a conditional instruction fails, the instruction:
Conditional instructions, except for conditional branches, must be inside an If-Then instruction
block. See
the vendor, the assembler might automatically insert an IT instruction if there are conditional
instructions outside the IT block.
The CBZ and CBNZ instructions are used to compare the value of a register against zero and
branch on the result.
This section describes:
• For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current
• For all other instructions that use labels, the value of the PC is the address of the current
• Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus
• immediately after the instruction that updated the flags
• after any number of intervening instructions that have not updated the flags.
• does not execute
• does not write any value to its destination register
• does not affect any of the flags
• does not generate any exception.
instruction plus 4 bytes.
instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it word-aligned.
or minus a number, or an expression of the form [PC, #number].
“Condition Flags”
“Condition Code Suffixes”
“Configuration and Control Register”
“”
for more information and restrictions when using the IT instruction. Depending on
. Some instructions update all flags, and some only update a subset. If a
Table 11-16
.
.
for a list of the suffixes to add to instructions to make
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
“Application Pro-

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