SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 131

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5.3.2
ARM DDI 0029G
Action of the processor in debug state
When the ARM7TDMI core enters debug state, the core forces nMREQ and SEQ to
indicate internal cycles. This action allows the rest of the memory system to ignore the
core and to function as normal. Because the rest of the system continues to operate, the
ARM7TDMI is forced to ignore aborts and interrupts.
The system must not change the BIGEND signal during debug because the debugger is
unaware that the core has been reconfigured.
nRESET must be held stable during debug because resetting the core while debugging
causes the debugger to lose track of the core.
When the system applies reset to the ARM7TDMI processor, with nRESET driven
LOW, the processor state changes with the debugger unaware that the core has reset.
When instructions are executed in debug state, all memory interface outputs, except
nMREQ and SEQ, change asynchronously to the memory system. For example, every
time a new instruction is scanned into the pipeline, the address bus changes. Although
this is asynchronous it does not affect the system, as nMREQ and SEQ are forced to
indicate internal cycles regardless of what the rest of the core is doing. The memory
controller must be designed to ensure that this asynchronous behavior does not affect
the rest of the system.
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Debug Interface
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