SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 268
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Debug in Depth
B.16
B-50
The debug status register
The debug status register is 5 bits wide. If it is accessed for a write, with the read/write
bit set, the status bits are written. If it is accessed for a read, with the read/write bit clear,
the status bits are read. The format of the debug status register is shown in Figure B-10.
The function of each bit in this register is as follows:
Bit 4
Bit 3
Bit 2
Bits 1:0
The structure of the debug control and status registers is shown in Figure B-11 on
page B-51.
TBIT
4
Copyright © 1994-2001. All rights reserved.
Enables TBIT to be read. This enables the debugger to determine
the processor state and therefore which instructions to execute.
Enables the debugger to determine if a memory access from the
debug state has completed.
Enables the state of the core interrupt enable signal, IFEN, to be
read. Enables the state of the NMREQ signal from the core,
synchronized to TCK, to be read. This enables the debugger to
determine that a memory access from the debug state has
completed.
Enable the values on the synchronized versions of DBGRQ and
DBGACK to be read.
cgenL
3
IFEN
2
Figure B-10 Debug status register format
DBGRQ
1
ARM DDI 0029G
DBGACK
0
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