SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 24

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Introduction
1.1
1.1.1
1-2
About the ARM7TDMI core
The instruction pipeline
The ARM7TDMI core is a member of the ARM family of general-purpose 32-bit
microprocessors. The ARM family offers high performance for very low power
consumption, and small size.
The ARM architecture is based on Reduced Instruction Set Computer (RISC)
principles. The RISC instruction set, and related decode mechanism are much simpler
than those of Complex Instruction Set Computer (CISC) designs. This simplicity gives:
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This section describes:
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The ARM7TDMI core uses a pipeline to increase the speed of the flow of instructions
to the processor. This allows several operations to take place simultaneously, and the
processing and memory systems to operate continuously.
A three-stage pipeline is used, so instructions are executed in three stages:
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The instruction pipeline is shown in Figure 1-1 on page 1-3.
a high instruction throughput
an excellent real-time interrupt response
a small, cost-effective, processor macrocell.
The instruction pipeline on page 1-2
Memory access on page 1-3
Memory interface on page 1-4.
EmbeddedICE Logic on page 1-4.
Fetch
Decode
Execute.
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