SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 246
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Debug in Depth
B-28
DBGACK
nMREQ
SEQ
D[31:0]
A[31:0]
CLK
You can see from Figure 5-3 on page 5-7 that the final memory access occurs in the
cycle after DBGACK goes HIGH, this is the point at which the cycle counter must be
disabled. Figure B-6 shows that the first memory access that the cycle counter has not
seen before occurs in the cycle after DBGACK goes LOW and so this is when the
counter must be re-enabled.
When a system speed access from debug state occurs, the core temporarily drops out of
debug state and so DBGACK can go LOW. If there are peripherals that are sensitive to
the number of memory accesses, they must be led to believe that the core is still in debug
state. By programming the EmbeddedICE macrocell control register, the value on
DBGACK can be forced to be HIGH.
Internal cycles
Note
Copyright © 1994-2001. All rights reserved.
N
Ab
S
Ab+4 Ab+8
Figure B-6 Debug exit sequence
S
ARM DDI 0029G
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