SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet
SAM9RL64
Specifications of SAM9RL64
Related parts for SAM9RL64
SAM9RL64 Summary of contents
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... EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and ® CompactFlash • LCD Controller (for AT91SAM9RL64 only) – Supports Passive or Active Displays – Bits per Pixel in TFT Mode bits per Pixel in STN Color Mode – 16M Colors in TFT Mode, Resolution Up t Support • ...
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One PLL 480 MHz Optimized for USB HS • Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Two Programmable External Clock Signals • Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level ...
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... Some features are not available for AT91SAM9R64 in the 144-ball BGA package. Separate block diagrams and PIO multiplexing are provided in this document. features and signals of AT91SAM9RL64 that are not available or partially available for AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified. ...
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Table 1-1. Feature PWM SPI SSC1 Touchscreen ADC TC TWI USART0 USART1 USART2 USART3 AT91SAM9R64/RL64 4 Unavailable or Partially Available Features and Signals in AT91SAM9R64 Full/Partial Signal Partial PWM2 NPCS2 Partial NPCS3 RF1 RK1 TD1 Full RD1 TK1 TF1 AD3YM ...
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Block Diagrams Figure 2-1. AT91SAM9R64 Block Diagram 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 5 ...
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... Figure 2-2. AT91SAM9RL64 Block Diagram AT91SAM9R64/RL64 6 6289CS–ATARM–28-May-09 ...
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Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIOM EBI I/O Lines Power Supply VDDIOP Peripherals I/O Lines Power Supply VDDUTMII USB UTMI+ Interface Power Supply VDDUTMIC USB UTMI+ Core Power Supply GNDUTMI USB UTMI ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NTRST Test Reset Signal NRST Microcontroller Reset TST Test Mode Select BMS Boot Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ External Interrupt Input FIQ Fast Interrupt Input ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NANDCS NAND Flash Chip Select NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDCS SDRAM Controller Chip Select BA0 - BA1 Bank ...
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Table 3-1. Signal Description List (Continued) Signal Name Function AC97RX AC97 Receive Signal AC97TX AC97 Transmit Signal AC97FS AC97 Frame Synchronization Signal AC97CK AC97 Clock signal TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A ...
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Table 3-1. Signal Description List (Continued) Signal Name Function DFSDM USB Device Full Speed Data - DFSDP USB Device Full Speed Data + DHSDM USB Device High Speed Data - DHSDP USB Device High Speed Data + 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Active ...
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... Package and Pinout The AT91SAM9R64 is available in a 144-ball BGA package. The AT91SAM9RL64 is available in a 217-ball LFBGA package. 4.1 144-ball BGA Package Outline Figure 4-1 Figure 4-1. 144-ball BGA Pinout (Top View) AT91SAM9R64/RL64 12 shows the orientation of the 144-ball BGA package ...
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Pinout Table 4-1. AT91SAM9R64 Pinout for 144-ball BGA Package Pin Signal Name Pin A1 DFSDM D1 A2 DHSDM D2 A3 XIN D3 A4 XOUT D4 A5 XIN32 D5 A6 XOUT32 D6 A7 TDO D7 A8 PA[31 PA[22] ...
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LFBGA Package Outline Figure 4-2 Figure 4-2. 217-ball LFBGA Pinout (Top View) AT91SAM9R64/RL64 14 shows the orientation of the 217-ball LFBGA package ...
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... Pinout Table 4-2. AT91SAM9RL64 Pinout for 217-ball LFBGA Package Pin Signal Name A1 DFSDM A2 DHSDP A3 VDDPLLB A4 XIN A5 XOUT A6 GNDPLLB A7 XOUT32 A8 GND A9 NRST A10 RTCK A11 PA[29] A12 PA[26] A13 PA[22] A14 PA[14] A15 PA[10] A16 PD[20] A17 PD[17] B1 DFSDP B2 DHSDM B3 VBG XIN32 B7 TST B8 GND B9 TMS B10 VDDCORE B11 ...
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Power Considerations 5.1 Power Supplies The AT91SAM9R64/RL64 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM ...
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Figure 5-1. VIN 5.2 Programmable I/O Lines Power Supplies The power supplies pins VDDIOM support two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The maximum speed is MCK ...
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I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors. TDO is an output, driven VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used ...
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DSP Instruction Extensions • 5-Stage Pipeline Architecture: – – – – – • 4-Kbyte Data Cache, 4-Kbyte Instruction Cache – – – – • Write Buffer – – – • Standard ARM v4 and v5 Memory Management ...
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Table 7-1. Master 3 Master 4 Master 5 7.3 Matrix Slaves The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave ...
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TWI0 Transmit Channel b. DBGU Transmit Channel c. USART3 Transmit Channel d. USART2 Transmit Channel e. USART1 Transmit Channel f. g. AC97 Transmit Channel h. SPI Transmit Channel TWI0 Receive Channel l. m. ADC Receive Channel ...
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Memories Figure 8-1. AT91SAM9R64/RL64 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 ...
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A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address ...
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Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the ...
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When accessed from the AHB, the internal Fast SRAM is single cycle accessible at full matrix speed (MCK). When accessed from the processor’s TCM Interface, they are also single cycle accessible at full processor speed. 8.1.1.2 Internal ROM The AT91SAM9R64/RL64 ...
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Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. For optimization purposes, nothing else is done. To speed up the boot ...
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SDRAM Controller • Supported devices: – Standard and Low Power SDRAM (Mobile SDRAM) – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path • Programming ...
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System Controller The System Controller is a set of peripherals, which allow handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface embeds also the registers allowing ...
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Block Diagram Figure 9-1. System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset backup_nreset SHDN WKUP RC OSC SLOW XIN32 CLOCK XOUT32 OSC XIN 12MHz MAIN OSC ...
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Reset Controller The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on VDDCORE. The Reset Controller is capable to return to the software the source of the last reset, either a general reset (VDDBU ...
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Figure 9-2. Clock Generator Block Diagram 9.6 Slow Clock Selection 9.6.1 Description The AT91SAM9R64/RL64 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an ...
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Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery Figure 9-3. AT91SAM9R64/RL64 Power Management Controller Block Diagram ...
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Two hundred year calendar • Programmable Periodic Interrupt • Alarm and update parallel load • Control of alarm and update Time/Calendar Data In 9.12 General-Purpose Backed-up Registers • Four 32-bit backup general-purpose registers 9.13 Advanced Interrupt Controller • Controls ...
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Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 9.15 Chip Identification • Chip ID: 0x019B03A0 • JTAG ID: ...
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... Timer Counter 2 Pulse Width Modulation Controller Touch Screen ADC Controller DMA Controller USB Device High Speed LCD Controller (AT91SAM9RL64 only) AC97 Controller Reserved Advanced Interrupt Controller Setting AIC, SYSIRQ, LCDC and IRQ bits in the clock set/clear registers of the PMC has no effect. ...
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... PIO_PSR resets high. This is the case for pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. The AT91SAM9RL64 and AT91SAM9R64 do not have the same peripheral signal multiplexing, each one follows. AT91SAM9R64/RL64 36 6289CS– ...
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... AT91SAM9RL64 PIO Multiplexing 10.4.1.1 AT91SAM9RL64 PIO Controller A Multiplexing Table 10-2. AT91SAM9RL64 Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 MC_DA0 PA1 MC_CDA PA2 MC_CK PA3 MC_DA1 PA4 MC_DA2 PA5 MC_DA3 PA6 TXD0 PA7 RXD0 PA8 SCK0 PA9 RTS0 PA10 CTS0 PA11 TXD1 PA12 ...
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... AT91SAM9RL64 PIO Controller B Multiplexing Table 10-3. AT91SAM9RL64 Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 TXD3 PB1 RXD3 PB2 A21/NANDALE PB3 A22/NANDCLE PB4 NANDOE PB5 NANDWE PB6 NCS3/NANDCS PB7 NCS4/CFCS0 PB8 CFCE1 PB9 CFCE2 PB10 A25/CFRNW PB11 A18 PB12 A19 PB13 A20 ...
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... AT91SAM9RL64 PIO Controller C Multiplexing Table 10-4. AT91SAM9RL64 Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 TF0 PC1 TK0 PC2 LCDMOD PC3 LCDCC PC4 LCDVSYNC PC5 LCDHSYNC PC6 LCDDOTCK PC7 LCDDEN PC8 LCDD0 PC9 LCDD1 PC10 LCDD2 PC11 LCDD3 PC12 LCDD4 PC13 LCDD5 ...
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... AT91SAM9RL64 PIO Controller D Multiplexing Table 10-5. AT91SAM9RL64 Multiplexing on PIO Controller D PIO Controller D I/O Line Peripheral A Peripheral B PD0 NCS2 PD1 AC97_FS PD2 AC97_CK SCK1 PD3 AC97_TX CTS3 PD4 AC97_RX RTS3 PD5 DTXD PWM2 PD6 AD4 PD7 AD5 PD8 NPCS2 PWM3 PD9 SCK2 NPCS3 PD10 ...
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AT91SAM9R64 PIO Multiplexing Note: In Table 10-6, Table 10-7, Table 10-8 AT91SAM9R64. 10.4.2.1 AT91SAM9R64 PIO Controller A Multiplexing Table 10-6. AT91SAM9R64 Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 MC_DA0 PA1 MC_CDA PA2 MC_CK ...
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AT91SAM9R64 PIO Controller B Multiplexing Table 10-7. AT91SAM9R64 Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 TXD3 PB1 RXD3 PB2 A21/NANDALE PB3 A22/NANDCLE PB4 NANDOE PB5 NANDWE PB6 NCS3/NANDCS PB7 NCS4/CFCS0 PB8 CFCE1 PB9 ...
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AT91SAM9R64 PIO Controller C Multiplexing Table 10-8. AT91SAM9R64 Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 TF0 PC1 TK0 PC2- NA PC31 10.4.2.4 AT91SAM9R64 PIO Controller D Multiplexing Table 10-9. AT91SAM9R64 Multiplexing on PIO ...
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Embedded Peripherals Overview 11.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – ...
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Optional break generation and detection – by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with ...
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Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all ...
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Endpoint 0: 64 bytes, 1 bank mode – Endpoint 1 & 2: 1024 bytes, 2 banks mode, HS isochronous capable, DMA – Endpoint 3 & 4: 1024bytes, 3 banks mode, DMA – Endpoint 5 & 6: 1024 bytes, 3 ...
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Package Drawings Figure 12-1. 144-ball BGA Package Drawing AT91SAM9R64/RL64 48 6289CS–ATARM–28-May-09 ...
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Figure 12-2. 217-ball LFBGA Package Drawing 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 49 ...
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... AT91SAM9R64/RL64 Ordering Information Table 13-1. AT91SAM9R64/RL64 Ordering Information Ordering Code MRL AT91SAM9R64-CU AT91SAM9RL64-CU AT91SAM9R64/RL64 50 Package A LFBGA144 A LFBGA217 Package Type Temperature Operating Range Green Industrial -40°C to 85°C Green 6289CS–ATARM–28-May-09 ...
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Revision History Doc. Rev Comments Product Overview: “Features” on page 1, removed mid-level Embedded Trace Macrocell feature “Features” on page 1, updated figures on CPU speed “Features” on page 1, updated SDIO and MMC version 6289CS Removed paragraph Section ...
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