SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet
SAM9RL64
Specifications of SAM9RL64
Related parts for SAM9RL64
SAM9RL64 Summary of contents
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... EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and ® CompactFlash • LCD Controller (for AT91SAM9RL64 only) – Supports Passive or Active Displays – Bits per Pixel in TFT Mode bits per Pixel in STN Color Mode – 16M Colors in TFT Mode, Resolution Up t Support • ...
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One PLL 480 MHz Optimized for USB HS • Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Two Programmable External Clock Signals • Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level ...
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... Some features are not available for AT91SAM9R64 in the 144-ball BGA package. Separate block diagrams and PIO multiplexing are provided in this document. features and signals of AT91SAM9RL64 that are not available or partially available for AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified. ...
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Table 1-1. Feature PWM SPI SSC1 Touchscreen ADC TC TWI USART0 USART1 USART2 USART3 AT91SAM9R64/RL64 4 Unavailable or Partially Available Features and Signals in AT91SAM9R64 Full/Partial Signal Partial PWM2 NPCS2 Partial NPCS3 RF1 RK1 TD1 Full RD1 TK1 TF1 AD3YM ...
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Block Diagrams Figure 2-1. AT91SAM9R64 Block Diagram 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 5 ...
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... Figure 2-2. AT91SAM9RL64 Block Diagram AT91SAM9R64/RL64 6 6289D–ATARM–3-Oct-11 ...
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Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIOM EBI I/O Lines Power Supply VDDIOP Peripherals I/O Lines Power Supply VDDUTMII USB UTMI+ Interface Power Supply VDDUTMIC USB UTMI+ Core Power Supply GNDUTMI USB UTMI ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NTRST Test Reset Signal NRST Microcontroller Reset TST Test Mode Select BMS Boot Mode Select DRXD Debug Receive Data DTXD Debug Transmit Data IRQ External Interrupt Input FIQ Fast Interrupt Input ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NANDCS NAND Flash Chip Select NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDCS SDRAM Controller Chip Select BA0 - BA1 Bank ...
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Table 3-1. Signal Description List (Continued) Signal Name Function AC97RX AC97 Receive Signal AC97TX AC97 Transmit Signal AC97FS AC97 Frame Synchronization Signal AC97CK AC97 Clock signal TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A ...
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Table 3-1. Signal Description List (Continued) Signal Name Function DFSDM USB Device Full Speed Data - DFSDP USB Device Full Speed Data + DHSDM USB Device High Speed Data - DHSDP USB Device High Speed Data + 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 Active ...
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... Package and Pinout The AT91SAM9R64 is available in a 144-ball BGA package. The AT91SAM9RL64 is available in a 217-ball LFBGA package. 4.1 144-ball BGA Package Outline Figure 4-1 Figure 4-1. 144-ball BGA Pinout (Top View) AT91SAM9R64/RL64 12 shows the orientation of the 144-ball BGA package ...
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Pinout Table 4-1. AT91SAM9R64 Pinout for 144-ball BGA Package Pin Signal Name Pin A1 DFSDM D1 A2 DHSDM D2 A3 XIN D3 A4 XOUT D4 A5 XIN32 D5 A6 XOUT32 D6 A7 TDO D7 A8 PA[31 PA[22] ...
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LFBGA Package Outline Figure 4-2 Figure 4-2. 217-ball LFBGA Pinout (Top View) AT91SAM9R64/RL64 14 shows the orientation of the 217-ball LFBGA package ...
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... Pinout Table 4-2. AT91SAM9RL64 Pinout for 217-ball LFBGA Package Pin Signal Name A1 DFSDM A2 DHSDP A3 VDDPLLB A4 XIN A5 XOUT A6 GNDPLLB A7 XOUT32 A8 GND A9 NRST A10 RTCK A11 PA[29] A12 PA[26] A13 PA[22] A14 PA[14] A15 PA[10] A16 PD[20] A17 PD[17] B1 DFSDP B2 DHSDM B3 VBG XIN32 B7 TST B8 GND B9 TMS B10 VDDCORE B11 ...
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Power Considerations 5.1 Power Supplies The AT91SAM9R64/RL64 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM ...
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Figure 5-1. VIN 5.2 Programmable I/O Lines Power Supplies The power supplies pins VDDIOM support two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The maximum speed is MCK ...
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I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors. TDO is an output, driven VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used ...
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DSP Instruction Extensions • 5-Stage Pipeline Architecture: – – – – – • 4-Kbyte Data Cache, 4-Kbyte Instruction Cache – – – – • Write Buffer – – – • Standard ARM v4 and v5 Memory Management ...
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Table 7-1. Master 3 Master 4 Master 5 7.3 Matrix Slaves The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave ...
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TWI0 Transmit Channel b. DBGU Transmit Channel c. USART3 Transmit Channel d. USART2 Transmit Channel e. USART1 Transmit Channel f. g. AC97 Transmit Channel h. SPI Transmit Channel TWI0 Receive Channel l. m. ADC Receive Channel ...
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Memories Figure 8-1. AT91SAM9R64/RL64 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 ...
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A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address ...
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Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the ...
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When accessed from the AHB, the internal Fast SRAM is single cycle accessible at full matrix speed (MCK). When accessed from the processor’s TCM Interface, they are also single cycle accessible at full processor speed. 8.1.1.2 Internal ROM The AT91SAM9R64/RL64 ...
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Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. For optimization purposes, nothing else is done. To speed up the boot ...
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SDRAM Controller • Supported devices: – Standard and Low Power SDRAM (Mobile SDRAM) – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path • Programming ...
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System Controller The System Controller is a set of peripherals, which allow handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface embeds also the registers allowing ...
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Block Diagram Figure 9-1. System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset backup_nreset SHDN WKUP RC OSC SLOW XIN32 CLOCK XOUT32 OSC XIN 12MHz MAIN OSC ...
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Reset Controller The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on VDDCORE. The Reset Controller is capable to return to the software the source of the last reset, either a general reset (VDDBU ...
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Figure 9-2. Clock Generator Block Diagram 9.6 Slow Clock Selection 9.6.1 Description The AT91SAM9R64/RL64 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an ...
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Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery Figure 9-3. AT91SAM9R64/RL64 Power Management Controller Block Diagram ...
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Two hundred year calendar • Programmable Periodic Interrupt • Alarm and update parallel load • Control of alarm and update Time/Calendar Data In 9.12 General-Purpose Backed-up Registers • Four 32-bit backup general-purpose registers 9.13 Advanced Interrupt Controller • Controls ...
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Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 9.15 Chip Identification • Chip ID: 0x019B03A0 • JTAG ID: ...
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... Timer Counter 2 Pulse Width Modulation Controller Touch Screen ADC Controller DMA Controller USB Device High Speed LCD Controller (AT91SAM9RL64 only) AC97 Controller Reserved Advanced Interrupt Controller Setting AIC, SYSIRQ, LCDC and IRQ bits in the clock set/clear registers of the PMC has no effect. ...
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... PIO_PSR resets high. This is the case for pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. The AT91SAM9RL64 and AT91SAM9R64 do not have the same peripheral signal multiplexing, each one follows. AT91SAM9R64/RL64 36 6289D– ...
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... AT91SAM9RL64 PIO Multiplexing 10.4.1.1 AT91SAM9RL64 PIO Controller A Multiplexing Table 10-2. AT91SAM9RL64 Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 MC_DA0 PA1 MC_CDA PA2 MC_CK PA3 MC_DA1 PA4 MC_DA2 PA5 MC_DA3 PA6 TXD0 PA7 RXD0 PA8 SCK0 PA9 RTS0 PA10 CTS0 PA11 TXD1 PA12 ...
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... AT91SAM9RL64 PIO Controller B Multiplexing Table 10-3. AT91SAM9RL64 Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 TXD3 PB1 RXD3 PB2 A21/NANDALE PB3 A22/NANDCLE PB4 NANDOE PB5 NANDWE PB6 NCS3/NANDCS PB7 NCS4/CFCS0 PB8 CFCE1 PB9 CFCE2 PB10 A25/CFRNW PB11 A18 PB12 A19 PB13 A20 ...
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... AT91SAM9RL64 PIO Controller C Multiplexing Table 10-4. AT91SAM9RL64 Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 TF0 PC1 TK0 PC2 LCDMOD PC3 LCDCC PC4 LCDVSYNC PC5 LCDHSYNC PC6 LCDDOTCK PC7 LCDDEN PC8 LCDD0 PC9 LCDD1 PC10 LCDD2 PC11 LCDD3 PC12 LCDD4 PC13 LCDD5 ...
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... AT91SAM9RL64 PIO Controller D Multiplexing Table 10-5. AT91SAM9RL64 Multiplexing on PIO Controller D PIO Controller D I/O Line Peripheral A Peripheral B PD0 NCS2 PD1 AC97_FS PD2 AC97_CK SCK1 PD3 AC97_TX CTS3 PD4 AC97_RX RTS3 PD5 DTXD PWM2 PD6 AD4 PD7 AD5 PD8 NPCS2 PWM3 PD9 SCK2 NPCS3 PD10 ...
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AT91SAM9R64 PIO Multiplexing Note: In Table 10-6, Table 10-7, Table 10-8 AT91SAM9R64. 10.4.2.1 AT91SAM9R64 PIO Controller A Multiplexing Table 10-6. AT91SAM9R64 Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 MC_DA0 PA1 MC_CDA PA2 MC_CK ...
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AT91SAM9R64 PIO Controller B Multiplexing Table 10-7. AT91SAM9R64 Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 TXD3 PB1 RXD3 PB2 A21/NANDALE PB3 A22/NANDCLE PB4 NANDOE PB5 NANDWE PB6 NCS3/NANDCS PB7 NCS4/CFCS0 PB8 CFCE1 PB9 ...
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AT91SAM9R64 PIO Controller C Multiplexing Table 10-8. AT91SAM9R64 Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A PC0 TF0 PC1 TK0 PC2- NA PC31 10.4.2.4 AT91SAM9R64 PIO Controller D Multiplexing Table 10-9. AT91SAM9R64 Multiplexing on PIO ...
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Embedded Peripherals Overview 11.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – ...
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Optional break generation and detection – by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with ...
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Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all ...
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Endpoint 0: 64 bytes, 1 bank mode – Endpoint 1 & 2: 1024 bytes, 2 banks mode, HS isochronous capable, DMA – Endpoint 3 & 4: 1024bytes, 3 banks mode, DMA – Endpoint 5 & 6: 1024 bytes, 3 ...
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AT91SAM9R64/RL64 48 6289D–ATARM–3-Oct-11 ...
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ARM926EJ-S Processor Overview 12.1 Overview The ARM926EJ-S processor is a member of the ARM9 sors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi- tasking applications where full memory management, high performance, low die size and ...
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Block Diagram Figure 12-1. ARM926EJ-S Internal Functional Block Diagram ETM Interface WDATA RDATA ARM9EJ-S EmbeddedICE Processor -RT INSTR ICE Interface 12.3 ARM9EJ-S Processor 12.3.1 ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a ...
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ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb ...
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Supervisor mode is a protected mode for the operating system • Abort mode is entered after a data or instruction prefetch abort • System mode is a privileged user mode for the operating system • Undefined mode is entered ...
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Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a pro- gram counter ...
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Figure 12-2. Status Register Format Figure 12-2 • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags • The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, ...
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The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. There is one exception in the priority scheme though, when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters ...
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Data processing instructions • Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). Table 12-2 Table 12-2. Mnemonic ...
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New ARM Instruction Set . Table 12-3. Mnemonic BXJ BLX SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB Notes: 12.3.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The ...
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Table 12-4. Mnemonic EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC 12.4 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • ...
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Table 12-5. Register Notes: 6289D–ATARM–3-Oct-11 CP15 Registers Name 8 TLB operations (2) 9 cache lockdown 9 TCM region 10 TLB lockdown 11 Reserved 12 Reserved (1) 13 FCSE PID (1) 13 Context ID 14 Reserved 15 Test configuration 1. Register ...
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CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) ...
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Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir- tual memory features required by operating systems like Symbian OS These virtual memory features are memory access permission controls and virtual to ...
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Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- fied Virtual Address), the access control logic ...
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A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a ...
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The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold words of data and ...
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Enabling and Disabling TCMs Prior to any enabling step, the user should configure the TCM sizes in HMATRIX TCM register. Then enabling TCMs is performed by using TCM region register (register 9) in CP15. The user should use the ...
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Table 8 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 12-7. Supported Transfers HBurst[2:0] Description SINGLE Single transfer INCR4 Four-word incrementing burst INCR8 Eight-word incrementing burst WRAP8 Eight-word wrapping burst 12.8.2 ...
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AT91SAM9R64/RL64 Debug and Test 13.1 Description The AT91SAM9R64/RL64 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug ...
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Block Diagram Figure 13-1. Debug and Test Block Diagram Boundary Port ARM9EJ-S ARM926EJ-S PDC TAP: Test Access Port AT91SAM9R64/RL64 68 ICE/JTAG TAP Reset and Test ICE-RT DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR TST DTXD DRXD 6289D–ATARM–3-Oct-11 ...
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Application Examples 13.3.1 Debug Environment Figure 13-2 on page 69 face is used for standard debugging functions, such as downloading code and single-stepping through the program. The Trace Port interface is used for tracing information. A software debug- ger ...
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Debug and Test Pin Description Table 13-1. Pin Name NTRST NRST TST TCK TDI TDO TMS RTCK JTAGSEL DRXD DTXD 13.5 Functional Description 13.5.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The ...
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JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction ...
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A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 13.5.6 ID Code Register Access: Read-only 31 30 VERSION PART NUMBER 7 6 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. ...
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AT91SAM9R64/RL64 Boot Program 14.1 Description The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. ...
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Figure 14-1. Boot Program Algorithm Flow Diagram Device Setup SD Card Boot No Timeout < NandFlash Boot No Timeout < SPI DataFlash Boot No Timeout < USB Enumeration Run SAM-BA Boot 14.3 Device Initialization ...
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Jump to SD Card Boot sequence Card Boot succeeds, perform a remap and jump to 0x0. 10. Jump to NAND Flash Boot sequence. If NAND Flash Boot succeeds, perform a remap and jump to 0x0. 11. Jump ...
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Figure 14-3. LDR Opcode Figure 14-4. B Opcode Unconditional instruction: 0xE for bits Load PC with PC relative addressing ...
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The DataFlash boot program supports all Atmel DataFlash devices. parameters to include in the ARM vector 6 for all devices. Table 14-1. Device AT45DB011 AT45DB021 AT45DB041 AT45DB081 AT45DB161 AT45DB321 AT45DB642 The DataFlash has a Status Register that determines all the ...
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Figure 14-6. Serial DataFlash Download Read the first 7 instructions (28 bytes). Read the DataFlash into the internal SRAM. Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded ...
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See on Valid Image Detection. 14.6.1 Supported NAND Flash Devices Any 8 or 16-bit NAND Flash devices. 14.7 SAM-BA Boot If no valid DataFlash device has been found during the DataFlash boot sequence, the ...
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Output: ‘>’ • Go (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal – Output: ‘>’ • Get Version (V): Return the SAM-BA boot version – Output: ‘>’ 14.7.1 DBGU ...
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Figure 14-7. Xmodem Transfer Example 14.7.3 USB High Speed Device Port A 480 MHz USB clock is necessary to use the USB High Speed Device port. It has been pro- grammed earlier in the device initialization procedure with UTMI PLL ...
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The device also handles some class requests defined in the CDC class. Table 14-4. Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE Unhandled requests are STALLed. 14.7.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint ...
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Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state. Table 14-5. Peripheral MCI MCI MCI MCI MCI MCI SPI SPI SPI SPI PIO ...
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AT91SAM9R64/RL64 84 6289D–ATARM–3-Oct-11 ...
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Reset Controller (RSTC) 15.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or ...
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Functional Description 15.3.1 Reset Controller Overview The Reset Controller is made NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset ...
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The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when ...
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Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed ...
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Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply pow- ers up, the POR output is ...
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User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR The NRST input signal is resynchronized with SLCK to insure proper behav- ior ...
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Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the ...
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Figure 15-7. Software Reset SLCK MCK Freq. Write RSTC_CR proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 SRCMP in RSTC_SR 15.3.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 ...
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Figure 15-8. Watchdog Reset SLCK MCK wd_fault proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 NRST (nrst_out) 15.3.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Backup ...
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SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the ...
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Reset Controller (RSTC) User Interface Table 15-1. Reset Controller (RSTC) Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset ...
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Reset Controller Control Register Register Name: RSTC_CR Access Type: Write-only – – – – – – • PROCRST: Processor Reset effect KEY is correct, resets ...
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Reset Controller Status Register Register Name: RSTC_SR Access Type: Read-only 31 30 – – – – – – – – • URSTS: User Reset Status high-to-low edge on NRST happened ...
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Reset Controller Mode Register Register Name: RSTC_MR Access Type: Read/Write – – – – – – • URSTEN: User Reset Enable 0 = The detection of a low level on the ...
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Real-time Timer (RTT) 16.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It gen- erates a periodic interrupt and/or triggers an alarm on a programmed value. 16.2 Block Diagram Figure 16-1. ...
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The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock advis- able to read this register twice at the ...
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Real-time Timer (RTT) User Interface 16.4.1 Register Mapping Table 16-1. Real-time Timer Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 Name Access RTT_MR Read/Write RTT_AR Read/Write RTT_VR Read-only RTT_SR ...
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Real-time Timer Mode Register Register Name: RTT_MR Access Type: Read/Write 31 30 – – – – • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time ...
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Real-time Timer Alarm Register Register Name: RTT_AR Access Type: Read/Write • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 16.4.4 Real-time Timer Value Register Register Name: ...
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Real-time Timer Status Register Register Name: RTT_SR Access Type: Read-only 31 30 – – – – – – – – • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred ...
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Periodic Interval Timer (PIT) 17.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt designed to offer maximum accuracy and efficient management, even for systems with long response time. 17.2 Block Diagram Figure 17-1. ...
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Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature built around two counters: a 20-bit CPIV counter and a ...
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Figure 17-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6289D–ATARM–3-Oct-11 MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR AT91SAM9R64/RL64 APB cycle APB cycle restarts MCK Prescaler ...
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Periodic Interval Timer (PIT) User Interface Table 17-1. Periodic Interval Timer (PIT) Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM9R64/RL64 108 Name Access PIT_MR Read/Write PIT_SR ...
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Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: Read/Write 31 30 – – – – • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the ...
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Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: Read-only PICNT Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the ...
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Watchdog Timer (WDT) 18.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period seconds ...
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Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a ...
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Figure 18-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault AT91SAM9R64/RL64 113 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 6289D–ATARM–3-Oct-11 ...
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Watchdog Timer (WDT) User Interface Table 18-1. Watchdog Timer Registers Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register 18.4.1 Watchdog Timer Control Register Register Name: WDT_CR Access Type: Write-only – – 15 ...
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Watchdog Timer Mode Register Register Name: WDT_MR Access Type: Read/Write Once 31 30 WDIDLEHLT WDDIS WDRPROC WDRSTEN 7 6 • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: ...
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Watchdog Timer Status Register Register Name: WDT_SR Access Type: Read-only 31 30 – – – – – – – – • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read ...
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Shutdown Controller (SHDWC) 19.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 19.2 Block Diagram Figure 19-1. Shutdown Controller Block Diagram Shutdown Controller SHDW_MR CPTWK0 WKMODE0 WKUP0 RTTWKEN ...
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Functional Description The Shutdown Controller manages the main power supply so supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. A typical application connects the pin SHDN to the shutdown input ...
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Shutdown Controller (SHDWC) User Interface Table 19-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register 6289D–ATARM–3-Oct-11 AT91SAM9R64/RL64 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only Reset - 0x0000_0003 0x0000_0000 119 ...
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Shutdown Control Register Register Name: SHDW_CR Access Type: Write-only – – – – – – • SHDW: Shutdown Command effect KEY is correct, asserts the ...
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Shutdown Mode Register Register Name: SHDW_MR Access Type: Read/Write 31 30 – – – – – CPTWK0 • WKMODE0: Wake-up Mode 0 WKMODE[1: • CPTWK0: ...
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Shutdown Status Register Register Name: SHDW_SR Access Type: Read-only 31 30 – – – – – – – – • WAKEUP0: Wake-up 0 Status wake-up event occurred on the corresponding ...
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Real-time Clock (RTC) 20.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calen- dar, complemented by a programmable periodic interrupt. The alarm ...
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The valid year range is 1900 to 2099, a two-hundred-year Gregorian calendar achieving full Y2K compliance. The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible ...
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Day (check range Hour (BCD checks: in 24-hour mode, check range and check that AM/PM flag is not set if RTC is set in 24-hour mode; in 12-hour mode check range 01 ...
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AT91SAM9R64/RL64 126 6289D–ATARM–3-Oct-11 ...
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RTC Control Register Name: RTC_CR Access Type: Read/Write 31 30 – – – – – – – – • UPDTIM: Update Request Time Register effect Stops the RTC ...
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RTC Mode Register Name: RTC_MR Access Type: Read/Write 31 30 – – – – – – – – • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected 12-hour mode is ...
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RTC Time Register Name: RTC_TIMR Access Type: Read/Write 31 30 – – – AMPM 15 14 – – • SEC: Current Second The range that can be set (BCD). The lowest ...
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RTC Calendar Register Name: RTC_CALR Access Type: Read/Write 31 30 – – DAY – • CENT: Current Century The range that can be set (BCD). The lowest four bits ...
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RTC Time Alarm Register Name: RTC_TIMALR Access Type: Read/Write 31 30 – – HOUREN AMPM 15 14 MINEN 7 6 SECEN • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. ...
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RTC Calendar Alarm Register Name: RTC_CALALR Access Type: Read/Write 31 30 DATEEN – MTHEN – – – – – • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded ...
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RTC Status Register Name: RTC_SR Access Type: Read-only 31 30 – – – – – – – – • ACKUPD: Acknowledge for Update 0 = Time and calendar registers cannot be updated. 1 ...
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RTC Status Clear Command Register Name: RTC_SCCR Access Type: Write-only 31 30 – – – – – – – – • ACKCLR: Acknowledge Clear effect Clears corresponding status ...
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RTC Interrupt Enable Register Name: RTC_IER Access Type: Write-only 31 30 – – – – – – – – • ACKEN: Acknowledge Update Interrupt Enable effect The acknowledge ...
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RTC Interrupt Disable Register Name: RTC_IDR Access Type: Write-only 31 30 – – – – – – – – • ACKDIS: Acknowledge Update Interrupt Disable effect The acknowledge ...
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RTC Interrupt Mask Register Name: RTC_IMR Access Type: Read-only 31 30 – – – – – – – – • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is ...
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RTC Valid Entry Register Name: RTC_VER Access Type: Read-only 31 30 – – – – – – – – • NVTIM: Non valid Time invalid data has been detected in ...
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External Bus Interface (EBI) 21.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, SDRAM and ECC Controllers ...
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Block Diagram 21.2.1 External Bus Interface 0 Figure 21-1 Figure 21-1. Organization of the External Bus Interface 0 Bus Matrix AHB Address Decoders AT91SAM9R64/RL64 140 shows the organization of the External Bus Interface 0. External Bus Interface 0 SDRAM ...
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I/O Lines Description Table 21-1. EBI I/O Lines Description Name Function EBI_D0 - EBI_D31 Data Bus EBI_A0 - EBI_A25 Address Bus EBI_NWAIT External Wait Signal EBI_NCS0 - EBI_NCS5 Chip Select Lines EBI_NWR0 - EBI_NWR3 Write Signals EBI_NRD Read Signal ...
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The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. Table 21-2 on page 142 EBI pins. Table 21-2. EBI_NWR1/NBS1/CFIOR EBI_A0/NBS0 EBI_A1/NBS2/NWR2 EBI_A[11:2] EBI_SDA10 EBI_A12 EBI_A[14:13] EBI_A[22:15] ...
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Application Example 21.4.1 Hardware Interface Table 21-3 on page 143 external devices for each Memory Controller. Table 21-3. EBI Pins and External Static Devices Connections 8-bit Static Signals: Device EBI_ Controller ...
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Table 21-4. EBI Pins and External Devices Connections Signals: EBI_ Controller D15 D16 - D31 A0/NBS0 A1/NWR2/NBS2 A2 - A10 A11 SDA10 A12 A13 - A14 A15 A16/BA0 A17/BA1 A18 - A20 A21/NANDALE A22/NANDCLE A23 ...
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Table 21-4. EBI Pins and External Devices Connections (Continued) Signals: EBI_ Controller SDCKE RAS CAS SDWE NWAIT (2) Pxx (2) Pxx (2) Pxx Note: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between ...
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Connection Examples Figure 21-2 Figure 21-2. EBI Connections to Memory Devices EBI D0-D31 RAS CAS SDCK SDCKE SDWE A0/NBS0 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NRD/NOE NWR0/NWE SDA10 A2-A15 A16/BA0 A17/BA1 A18-A25 NCS0 NCS1/SDCS NCS2 NCS3 NCS4 NCS5 21.5 Product Dependencies 21.5.1 ...
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ECC Controller (ECC) • a chip select assignment feature that assigns an AHB address space to the external devices • a multiplex controller circuit that shares the pins between the different Memory Controllers • programmable CompactFlash support logic ...
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I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish I/O mode, common memory mode, attribute memory mode and True IDE mode. ...
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The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer to the Static Memory Controller section. Table 21-6. CFCE1 and CFCE2 Truth Table Mode CFCE2 Attribute Memory NBS1 NBS1 Common ...
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Figure 21-4. CompactFlash Read/Write Control Signals External Bus Interface SMC Table 21-7. CompactFlash Mode Selection Mode Base Address Attribute Memory Common Memory I/O Mode True IDE Mode 21.6.6.4 Multiplexing of CompactFlash Signals on EBI Pins Table 21-8 on page 150 ...
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Table 21-9. Shared CompactFlash Interface Multiplexing Pins NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW A25/CFRNW 21.6.6.5 Application Example Figure 21-5 on page 152 CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc- tion and the output ...
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Figure 21-5. CompactFlash Application Example EBI D[15:0] A25/CFRNW NCS4/CFCS0 CD (PIO) A[10:0] A22/REG NOE/CFOE NWE/CFWE NWR1/CFIOR NWR3/CFIOW CFCE1 CFCE2 NWAIT 21.6.7 NAND Flash Support External Bus Interface integrates circuitry that interfaces to NAND Flash devices. 21.6.7.1 External Bus Interface The ...
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Figure 21-6. NAND Flash Signal Multiplexing on EBI Pins SMC NWR0_NWE 21.6.7.2 NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI ...
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Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability. 21.7.1 16-bit SDRAM 21.7.1.1 Hardware Configuration D[0..15] A[0..14] (Not used A12) 21.7.1.2 Software ...
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SDRAM 21.7.2.1 Hardware Configuration D[0..31] A[0..14] (Not used A12 A10 A11 SDA10 SDA10 A13 BA0 BA0 BA1 BA1 A14 SDCKE SDCKE SDCK SDCK 1%6 A0 1%6 CFIOR_NBS1_NWR1 CAS CAS RAS ...
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NAND Flash 21.7.3.1 Hardware Configuration D[0..7] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 21.7.3.2 Software Configuration The following configuration has to be performed: • Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A ...
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NAND Flash 21.7.4.1 Hardware Configuration D[0..15] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 21.7.4.2 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the mode ...
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NOR Flash on NCS0 21.7.5.1 Hardware Configuration D[0..15] A[1..22] NRST NWE NCS0 NRD 21.7.5.2 Software Configuration The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit ...
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Compact Flash 21.7.6.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 A25/CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) &$5' '(7(&7 A[0..10] A10 ...
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Software Configuration The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located ...
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Compact Flash True IDE 21.7.7.1 Hardware Configuration D[0..15] D15 D14 D13 D12 D11 D10 A25/CFRNW 4 CFCSx (CFCS0 or CFCS1) 5 (ANY PIO) &$5' '(7(&7 A[0..10] A10 A9 A8 ...
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Software Configuration The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located ...
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Static Memory Controller (SMC) 22.1 Description The Static Memory Controller (SMC) generates the signals that control the access to the exter- nal memory devices or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The 32-bit ...
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Application Example 22.4.1 Hardware Interface Figure 22-1. SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NCS0 NCS1 NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 A2 - A25 Static Memory Controller 22.5 Product Dependencies 22.5.1 I/O Lines ...
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External Memory Mapping The SMC provides address lines, A[25:0]. This allows each chip select line to address Mbytes of memory. If the physical memory device connected on one chip select is smaller than ...
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Figure 22-3. Memory Connection for an 8-bit Data Bus Figure 22-4. Memory Connection for a 16-bit Data Bus Figure 22-5. Memory Connection for a 32-bit Data Bus SMC AT91SAM9R64/RL64 166 D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] D[15:0] A[19:2] ...
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Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. Note that the SMC does not allow boot in Byte Write Access mode. • For 16-bit devices: ...
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Figure 22-6. Connection 8-bit Devices on a 16-bit Bus: Byte Write Option 22.7.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus ...
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Figure 22-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) SMC Table 22-3. SMC Multiplexed Signal Translation Signal Name Device Type 1x32-bit Byte Access Type (BAT) Byte Select NBS0_A0 NBS0 NWE_NWR0 NWE NBS1_NWR1 NBS1 NBS2_NWR2_A1 ...
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Read Waveforms The read cycle is shown on The read cycle starts with the address setting on the memory address bus, i.e.: {A[25:2], A1, A0} for 8-bit devices {A[25:2], A1} for 16-bit devices A[25:2] for 32-bit devices. Figure 22-8. ...
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NCS Waveform Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: ...
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Figure 22-9. No Setup, No Hold On NRD and NCS Read Signals MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] 22.8.1.5 Null Pulse Programming null pulse is not permitted. Pulse must be at least set null ...
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Figure 22-10. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] 22.8.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 22-11 the falling edge of ...
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Write Waveforms The write protocol is similar to the read protocol depicted in starts with the address setting on the memory address bus. 22.8.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse ...
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Write Cycle The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle ...
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Write Mode The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indi- cates which signal controls the write operation. 22.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1): Figure 22-14 put on the bus during the ...
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Figure 22-15. WRITE_MODE = 0. The write operation is controlled by NCS MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 22.8.5 Coding Timing Parameters All timing parameters are defined for one chip ...
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Reset Values of Timing Parameters Table 22-5 Table 22-5. Register SMC_SETUP SMC_PULSE SMC_CYCLE WRITE_MODE READ_MODE 22.8.7 Usage Restriction The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger ...
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Figure 22-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWE NCS0 NCS2 D[31:0] 22.9.2 Early Read Wait State In some cases, the SMC ...
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Figure 22-17. Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NRD D[31:0] Figure 22-18. Early Read Wait State: NCS Controlled Write with No Hold Followed ...
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Figure 22-19. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 internal write controlling signal external write controlling signal (NWE) D[31:0] 22.9.3 Reload User Configuration ...
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Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred read to write wait state in this document. ...
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Data Float Wait States Some memory devices are slow to release the external bus. For such devices necessary to add wait states (data float wait states) after a read access: • before starting a read access to ...
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Figure 22-20. TDF Period in NRD Controlled Read Access (TDF = 2) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NRD NCS D[31:0] Figure 22-21. TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, ...
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TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait ...
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Figure 22-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects MCK 25:2] A[ NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) read2 controlling signal (NRD) D[31:0] read1 cycle ...
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Figure 22-25. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 controlling signal (NWE) D[31:0] TDF_CYCLES = 5 22.11 ...
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Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchroniza- tion of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the ...
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Figure 22-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK [25:2] A NBS0, NBS1, NBS2, NBS3, A0,A1 4 NCS 1 NRD NWAIT internally synchronized NWAIT signal 6289D–ATARM–3-Oct-11 FROZEN STATE ...
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Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, ...
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Figure 22-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS NRD NWAIT internally synchronized NWAIT signal 6289D–ATARM–3-Oct- Read cycle EXNW_MODE = ...
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NWAIT Latency and Read/write Timings There may be a latency between the assertion of the read/write controlling signal and the asser- tion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must ...
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Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow ...
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Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode ...
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Figure 22-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS SLOW CLOCK ...
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Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field ...
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NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses within the page are defined using the NRD_PULSE parameter. In page mode, the programming of the read timings is described in Table 22-8. Parameter READ_MODE NCS_RD_SETUP NCS_RD_PULSE NRD_SETUP ...
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Figure 22-35. Access to Non-sequential Data within the Same Page MCK A[25:3] A[2], A1, A0 NRD NCS D[7:0] 6289D–ATARM–3-Oct-11 Page address A1 D1 NRD_PULSE NCS_RD_PULSE AT91SAM9R64/RL64 NRD_PULSE 198 ...
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Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in gram the parameters of the external device connected on it bytes (0x10) are required per chip select. The user must complete writing ...
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SMC Setup Register Register Name: SMC_SETUP[0 ..5] Access Type: Read/Write 31 30 – – – – – – – – • NWE_SETUP: NWE Setup Length The NWE signal setup length is defined as: ...