SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 886

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

47.2.6
47.2.6.1
47.2.6.2
47.2.6.3
47.2.6.4
886
AT91SAM9R64/RL64
Serial Synchronous Controller (SSC)
SSC: Transmitter Limitations in Slave Mode
SSC: Periodic Transmission Limitations in Master Mode
SSC: Unexpected RK clock cycle when RK outputs a clock during data transfer
SSC: Incorrect first RK clock cycle when RK outputs a clock during data transfer
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when start of edge (rising or falling) of synchro with a Start Delay equal to zero.
None.
If Last Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent.
None.
When the SSC receiver is used in the following configuration:
then, at the end of the data, the RK pin is set in high impedance which may be interpreted as an
unexpected clock cycle.
Enable the pull-up on RK pin.
When the SSC receiver is used in the following configuration:
• the internal clock divider is used (CKS =0 and DIV different from 0),
• RK pin set as output and provides the clock during data transfer (CKO=2)
• data sampled on RK falling edge (CKI =0)
• RX clock is divided clock (CKS =0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO=2)
• data sampled on RK falling edge (CKI =0)
;prepare power down command
;prepare proc_reset and periph_reset
;perform power down command
;perform proc_reset and periph_reset (in the ARM pipeline)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
LDR r0, =AT91C_SDRAMC_LPR
LDR r1, =2
LDR r2, =AT91C_RSTC_RCR
LDR r3, =0xA5000005
STR r1, [r0]
STR r3, [r2]
END
6289D–ATARM–3-Oct-11