SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 3

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

•
•
•
•
1. Description
6289D–ATARM–3-Oct-11
SAM-BA
IEEE
Required Power Supplies:
Available in a 144-ball BGA (AT91SAM9R64) and a 217-ball LFBGA (AT91SAM9RL64) Package
– Master, Multi-master and Slave Mode Operation
– Bit Rate: Up to 400 Kbits
– General Call Supported in Slave Mode
– Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only
– Default Boot Program
– Interface with SAM-BA Graphic User Interface
– 1.08 to 1.32V for VDDCORE, VDDUTMIC, VDDPLLB and VDDBU
– 3.0V to 3.6V for VDDPLLA, VDDANA, VDDUTMII and VDDIOP
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM
(TWI0 only)
®
1149.1 JTAG Boundary Scan on All Digital Pins
®
Boot Assistant
The AT91SAM9R64/RL64 device is based on the integration of an ARM926EJ-S processor with
a large fast SRAM and a wide range of peripherals.
The AT91SAM9R64/RL64 embeds one USB Device High Speed Controller, one LCD Controller
(for AT91SAM9RL64 only), one AC97 controller, a 2-channel DMA Controller, four USARTs, two
SSCs, one SPI, two TWIs, three Timer Counter channels, a 4-channel PWM generator, one Mul-
timedia Card interface and a 6-channel Analog-to-digital converter that also provides resistive
touch screen management.
The AT91SAM9R64/RL64 is architectured on a 6-layer bus matrix. It also features an External
Bus Interface capable of interfacing with a wide range of memory and peripheral devices.
Some features are not available for AT91SAM9R64 in the 144-ball BGA package.
Separate block diagrams and PIO multiplexing are provided in this document.
features and signals of AT91SAM9RL64 that are not available or partially available for
AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified.
Table 1-1.
Feature
AC97
EBI
LCDC
Unavailable or Partially Available Features and Signals in AT91SAM9R64
Full/Partial
Full
Partial
Full
Signal
AC97FS
AC97CK
AC97TX
AC97RX
D16-D31
NCS2
NCS5/CFCS1
LCDMOD
LCDCC
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
LCDD0-LCDD23
AT91SAM9R64/RL64
Peripheral A
PD1
PD2
PD3
PD4
PB16-PB31
PD0
PD13
PC2
PC3
PC4
PC5
PC6
PC7
PC8-PC31
Peripheral B
-
-
-
Table 1-1
lists the
3