SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 578

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

37.3.4.3
6289D–ATARM–3-Oct-11
Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4)
Note:
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of Linked List Items (otherwise known as buffer descriptors) in mem-
3. Write the channel configuration information into the DMAC_CFGx register for channel
4. Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory
5. Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory
6. Make sure that the LLI.DMAC_SADDRx/LLI.DMAC_DADDRx register locations of all
7. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register
8. If source picture-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), pro-
9. If destination picture-in-picture is enabled (DMAC_CTRLBx.DST_PIP is enabled), pro-
10. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
11. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in
12. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
13. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit, where n
14. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
15. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to sys-
ory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx
registers location of the buffer descriptor for each LLI in memory (see
page
h. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_WIDTH field.
– ii. Transfer width for the destination in the DST_WIDTH field.
– iii. Source AHB master interface layer in the SIF field where source resides.
– iv. Destination AHB master interface layer in the DIF field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
x.
(except the last) are set as shown in Row 4 of
LLI.DMAC_CTRLBx register of the last Linked List Item must be set as described in
Row 1 of
list items.
(except the last) are non-zero and point to the base address of the next Linked List
Item.
LLI entries in memory point to the start source/destination buffer address preceding
that LLI fetch.
locations of all LLI entries in memory are cleared.
gram the DMAC_SPIPx register for channel x.
gram the DMAC_DPIPx register for channel x.
ing the status register: DMAC_EBCISR.
Table 37-1 on page
Linked List item.
is the channel number. The transfer is performed.
tem memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF)
where it was originally fetched, that is, the location of the DMAC_CTRLAx register of
The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the
DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx chan-
nel registers from the DMAC_DSCRx(0).
579) for channel x. For example, in the register, you can program the following:
Table
37-1.
575.
Figure 37-4 on page 574
Table 37-1 on page
shows a Linked List example with two
AT91SAM9R64/RL64
575. The
Figure 37-5 on
578