ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 59

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

7701E–AVR–02/11
Figure 12-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The
latch is closed when the clock is low, and goes transparent when the clock is high, as indi-
cated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the
system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock
edge. As indicated by the two arrows t
be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
positive edge of the clock. In this case, the delay t
clock period.
Figure 12-4. Synchronization when Reading a Software Assigned Pin Value
INSTRUCTIONS
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
SYSTEM CLK
SYNC LATCH
Figure 12-4 on page
PINxn
PINxn
r17
r16
r17
Atmel ATtiny24/44/84 [Preliminary]
out PORTx, r16
59. The out instruction sets the “SYNC LATCH” signal at the
XXX
pd,max
and t
t
pd, max
0x00
0x00
pd,min
XXX
nop
pd
t
pd
through the synchronizer is one system
t
, a single signal transition on the pin will
0xFF
pd, min
in r17, PINx
in r17, PINx
0xFF
0xFF
59