ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet
ATmega88PA Automotive
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ATmega88PA Automotive Summary of contents
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Features • High Performance, Low Power AVR • Advanced RISC Architecture – 131 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation – 16MIPS Throughput at 16MHz – ...
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Pin Configurations ® Figure 1-1. Pinout Atmel ATmega48PA/88PA/168PA 32 TQFP Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 Atmel ATmega48PA/88PA/168PA [Preliminary PC1 (ADC1/PCINT9) ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 1.1 Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers ...
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Port D (PD7:0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 2. Overview The Atmel the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATmega48PA/88PA/168PA achieves throughputs approaching 1 MIPS per- MHz allowing the system designer to optimize power consumption versus ...
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The Atmel In-System Programmable Flash with Read-While-Write capabilities, 256/512/512K bytes EEPROM, 512/1K/1K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 3. Automotive Quality Grade The Atmel the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the ...
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AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access mem- ories, perform calculations, ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The fast-access Register File contains 32 x 8-bit general purpose working registers with a sin- gle clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typical ALU operation, two operands are output ...
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Status Register The Status Register contains information about the result of the most recently executed arith- metic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The ...
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The X-register, Y-register, and Z-register The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indi- rect address registers X, Y, and ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 7.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 7.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The ...
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Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Assembly Code Example C Code Example When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example C Code Example ...
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AVR Memories 8.1 Overview This section describes the different memories in the Atmel AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the Atmel ATmega48PA/88PA/168PA features an EEPROM Memory for data ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 8-1. Figure 8-2. 9223B–AVR–09/11 Program Memory Map Atmel ATmega48PA Program Memory Application Flash Section Program Memory Map Atmel ATmega88PA, Atmel ATmega168PA Program Memory Application Flash Section Boot Flash Section 0x0000 0x7FF 0x0000 0x0FFF/0x1FFF/0x3FFF 17 ...
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SRAM Data Memory Figure 8-3 The Atmel ATmega48PA/88PA/168PA is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 8.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 8-4. 8.4 EEPROM Data Memory The Atmel ory. It ...
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Preventing EEPROM Corruption During periods of low V too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 8.6 Register Description 8.6.1 EEARH and EEARL – The EEPROM Address Register Bit 0x22 (0x42) 0x21 (0x41) Read/Write Initial Value • Bits 15:9] – Reserved These bits are reserved bits in the Atmel zero. • Bits 8:0 ...
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While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 8-1. EEPM1 • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, ...
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Assembly Code Example C Code Example Atmel ATmega48PA/88PA/168PA [Preliminary] 24 EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execu- tion of these functions. Assembly Code Example EEPROM_read: C ...
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System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 9.1.3 Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 9.1.4 Asynchronous Timer Clock – clk The Asynchronous Timer clock allows ...
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Table 9-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V The delay will not monitor the actual voltage and it will be required to select a ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3...1 as shown in 9-3 on page Table 9-3. Frequency Range Notes: ...
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Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in quartz crystal or a ceramic resonator may be used. ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Table 9-6. Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, ...
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The Low-frequency Crystal Oscillator provides an internal load capacitance, see each TOSC pin. Table 9-8. ATmega48PA/88PA/168PA The capacitance (Ce + Ci) needed at each TOSC pin can be calculated by using where: – optional ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 9.6 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8.0MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 29-3 on page 317 ...
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Internal Oscillator The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz. The fre- quency is nominal at 3V and 25°C. This clock may be select as the system clock by programming the CKSEL ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table Table 9-16. Power Conditions BOD enabled Fast rising power Slowly rising power When applying an external clock ...
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System Clock Prescaler The Atmel ATmega48PA/88PA/168PA has a system clock prescaler, and the system clock can be divided by setting the can be used to decrease the system clock frequency and the power consumption when the requirement for processing ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 9.12 Register Description 9.12.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL[7:0]: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove ...
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The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 10. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion ...
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BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses - see page 297 sleep period. To save power possible to disable the BOD by software for some of the sleep modes, see the ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 10.5 Power-down Mode When the SM2...0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external inter- rupts, the 2-wire Serial Interface ...
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Power Reduction Register The Power Reduction Register (PRR), see provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 10.10.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage ...
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Register Description 10.11.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits [7:4]: Reserved These bits are unused in the Atmel zero. • ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 10.11.2 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 6 – BODS: BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep, see ...
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Bit 2 – PRSPI: Power Reduction Serial Peripheral Interface If using debugWIRE On-chip Debug System, this bit should not be written to one. Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 11. System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. For Atmel must be a JMP – Absolute ...
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Figure 11-1. Reset Logic BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER RSTDISBL 11.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in whenever V Reset, as well as to detect ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 11-2. MCU Start-up, RESET Tied to V Figure 11-3. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL 11.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than ...
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Brown-out Detection The Atmel monitoring the V level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 11.7 Internal Voltage Reference The Atmel ence is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 11.7.1 Voltage Reference Enable Signals and Start-up Time The voltage ...
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Figure 11-7. Watchdog Timer In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Assembly Code Example C Code Example Notes: 9223B–AVR–09/11 (1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR r16, MCUSR in r16, (0xff & (0<<WDRF)) andi out MCUSR, r16 ...
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The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example C Code Example Notes: Atmel ATmega48PA/88PA/168PA [Preliminary] 54 (1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 11.9 Register Description 11.9.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x34 (0x54) Read/Write Initial Value • Bit 7:4: Reserved These bits are unused ...
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WDTCSR – Watchdog Timer Control Register Bit (0x60) Read/Write Initial Value • Bit 7 – WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con- figured for ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] • Bit 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler and 0 The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods ...
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Interrupts This section describes the specifics of the interrupt handling as performed in the Atmel ATmega48PA/88PA/168PA. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page The interrupt vectors in the Atmel ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The most typical and general program setup for the Reset and Interrupt Vector Addresses in Atmel Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 ...
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Interrupt Vectors in the Atmel ATmega88PA Table 12-2. Reset and Interrupt Vectors in the Atmel ATmega88PA (2) Vector No. Program Address (1) 1 0x000 2 0x001 3 0x002 4 0x003 5 0x004 6 0x005 7 0x006 8 0x007 9 ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Table 12-3. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in the Atmel Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0X008 0x009 0x00A 0x00B 0x00C ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 0xC19 ; 0xC1A 0xC1B 0xC1C 0xC1D 0xC1E 0xC1F 12.3 Interrupt Vectors in the Atmel ATmega168PA Table 12-4. Reset and Interrupt Vectors in the Atmel ATmega168PA VectorNo. Program Address (1) 1 0x0000 2 0x0002 3 0x0004 4 0x0006 ...
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Table 12-5 on page 64 tions of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 0x0033RESET: 0x0034 0x0035 0x0036 0x0037 0x0038 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most ...
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When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Interrupts will automatically be disabled while this sequence is executed. Interrupts are dis- abled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not ...
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External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23...0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23...0 pins are configured as ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 13.2 Register Description 13.2.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit (0x69) Read/Write Initial Value • Bit 7:4 – Reserved These bits are ...
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EIMSK – External Interrupt Mask Register Bit 0x1D (0x3D) Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused bits in the Atmel zero. • Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 13.2.4 PCICR – Pin Change Interrupt Control Register Bit (0x68) Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused bits in the Atmel zero. • Bit 2 – PCIE2: Pin Change Interrupt Enable 2 ...
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Bit 0 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 14. I/O-Ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 14-2. General Digital I/O Pxn Note: 14.2.1 Configuring the Pin Each port pin ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 14.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. ...
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indi- cated by the shaded region of ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Assembly Code Example C Code Example Note: 14.2.5 Digital Input Enable and Sleep Modes As shown in Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save ...
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Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 14.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified ridden by alternate functions. The overriding signals may not be ...
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Table 14-2 Figure 14-5 on page 79 generated internally in the modules having the alternate function. Table 14-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 14.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 14-3. Port Pin The alternate pin configuration is as follows: • XTAL2/TOSC2/PCINT7 – Port B, Bit 7 XTAL2: Chip clock ...
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XTAL1/TOSC1/PCINT6 – Port B, Bit 6 XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] • SS/OC1B/PCINT2 – Port B, Bit 2 SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB2 Slave, the SPI ...
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Table 14-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Notes: Table 14-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Atmel ATmega48PA/88PA/168PA [Preliminary] 84 Overriding Signals for Alternate Functions in PB7...PB4 ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 14.3.2 Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 14-6. The alternate pin configuration is as follows: • RESET/PCINT14 – Port C, Bit 6 RESET, Reset pin: When the ...
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SDA/ADC4/PCINT12 – Port C, Bit 4 SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PC4 is disconnected from the port and becomes the Serial Data I/O ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Table 14-7 shown in Table 14-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: Table 14-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 9223B–AVR–09/11 and Table 14-8 ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 14-9. The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, Bit 7 AIN1, Analog Comparator Negative Input. Configure the port ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] • T1/OC0B/PCINT21 – Port D, Bit 5 T1, Timer/Counter1 counter source. OC0B, Output Compare Match output: The PD5 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PD5 pin has to be ...
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Table 14-10 shown in Table 14-10. Overriding Signals for Alternate Functions PD7...PD4 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 14-11. Overriding Signals for Alternate Functions in PD3...PD0 Signal Name PUOE PUO DDOE DDOV PVOE ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 14.4 Register Description 14.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value Note: • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are ...
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PORTD – The Port D Data Register Bit 0x0B (0x2B) Read/Write Initial Value 14.4.9 DDRD – The Port D Data Direction Register Bit 0x0A (0x2A) Read/Write Initial Value 14.4.10 PIND – The Port D Input Pins Address Bit 0x09 ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 15. 8-bit Timer/Counter0 with PWM 15.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • ...
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Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Depending of the mode of operation used, the counter is cleared, incremented, or decre- mented at each timer clock (clk source, selected by the Clock Select bits ...
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Figure 15-3 Figure 15-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com- pare (FOC0x) ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 15-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler ...
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In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in histogram for ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The wave- form generated will have a ...
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In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 15-9 Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOVn Figure 15-10 mode and PWM mode, where OCR0A is TOP. Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF0x, ...
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Register Description 15.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Table 15-4 correct PWM mode. Table 15-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are ...
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Table 15-7 correct PWM mode. Table 15-7. COM0B1 Note: • Bits 3, 2 – Reserved These bits are reserved bits in the Atmel zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 15.9.2 TCCR0B – Timer/Counter Control Register B Bit 0x25 (0x45) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, ...
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Table 15-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 15.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register Bit (0x6E) Read/Write Initial Value • Bits 7:3 – Reserved These bits are reserved bits in the Atmel zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt ...
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Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 16. 16-bit Timer/Counter1 with PWM 16.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler ...
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Figure 16-1. 16-bit Timer/Counter Block Diagram Note: 16.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Reg- ister (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Gen- erator to generate a PWM or variable frequency output ...
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Assembly Code Examples C Code Examples Note important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Assembly Code Example C Code Example Note: The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the ...
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Assembly Code Example C Code Example Note: The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. 16.3.1 Reusing the Temporary High Byte Register If writing to more than one 16-bit register ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 16.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2. Counter Unit Block Diagram Signal description (internal signals): The 16-bit counter is mapped into two 8-bit I/O memory ...
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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 16.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- tion mode (WGM13:0) bits must be set ...
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Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering ...
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Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 16.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 16.8.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no action on ...
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The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 16-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 16.9.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM ...
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When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 16.9.4 Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct ...
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The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 16.9.5 Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13 provides a high resolution phase and frequency correct PWM waveform ...
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Figure 16-9. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the ...
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Figure 16-12 and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 16.11 Register Description 16.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B ...
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Table 16-3 correct or the phase and frequency correct, PWM mode. Table 16-3. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the count- ing sequence ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Table 16-4. Waveform Generation Mode Bit Description WGM12 Mode WGM13 (CTC1) (PWM11 ...
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Bit 5 – Reserved This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 16.11.4 TCNT1H and TCNT1L – Timer/Counter1 Bit (0x85) (0x84) Read/Write Initial Value The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit ...
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ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 7, 6 – Reserved These bits are unused bits in the Atmel zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag ...
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Timer/Counter0 and Timer/Counter1 Prescalers “8-bit Timer/Counter0 with PWM” on page 93 111 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 17.1 Internal Clock Source The ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half ...
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Register Description 17.4.1 GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler ...
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Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 18.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. ure 18-2 on page 145 Figure 18-2. Counter Unit Block Diagram Signal description (internal signals): Depending on the mode of operation ...
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Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 18.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x ...
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Figure 18-4. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 18.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The ...
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An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 18-6. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for ...
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Phase Correct PWM Mode The phase correct PWM mode (WGM22 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting ...
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Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk T2 replaced by the Timer/Counter Oscillator clock. The figures include information on when Inter- rupt Flags are set. figure shows the count ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 18-11 Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with 18.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking ...
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If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions must be taken if the user wants to re-enter one of these modes: If re-entering sleep mode within the TOSC1 cycle, the ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 18.10 Timer/Counter Prescaler Figure 18-12. Prescaler for Timer/Counter2 The clock source for Timer/Counter2 is named clk main system I/O clock clk nously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter ...
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Register Description 18.11.1 TCCR2A – Timer/Counter Control Register A Bit (0xB0) Read/Write Initial Value • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Table 18-4 correct PWM mode. Table 18-4. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are ...
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Table 18-7 correct PWM mode. Table 18-7. COM2B1 Note: • Bits 3, 2 – Reserved These bits are reserved bits in the Atmel zero. • Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 18.11.2 TCCR2B – Timer/Counter Control Register B Bit (0xB1) Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ...
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Table 18-9. CS22 If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 18.11.3 TCNT2 ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 18.11.6 TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit (0x70) Read/Write Initial Value • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the ...
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Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] • Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by ...
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SPI – Serial Peripheral Interface 19.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The interconnection between Master and Slave CPUs with SPI is shown in page Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to ...
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In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low periods: Longer than 2 CPU clock cycles. ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Assembly Code Example C Code Example Note: 9223B–AVR–09/11 (1) SPI_MasterInit: ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) ldi SPCR,r17 out ret SPI_MasterTransmit: ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example C Code Example Note: Atmel ATmega48PA/88PA/168PA [Preliminary] 170 (1) SPI_SlaveInit: ; Set MISO output, all others input ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 19.3 SS Pin Functionality 19.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output ...
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Figure 19-3. SPI Transfer Format with CPHA = 0 Figure 19-4. SPI Transfer Format with CPHA = 1 Atmel ATmega48PA/88PA/168PA [Preliminary] 172 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 19.5 Register Description 19.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the ...
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Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 19.5.3 SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register ...
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USART0 20.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 20-1. USART Block Diagram Note: 20.3 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master ...
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Figure 20-2 Figure 20-2. Clock Generation Logic, Block Diagram Signal description: 20.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Table 20-1 lating the UBRRn value for each mode of operation using an internally generated clock source. Table 20-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode ...
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Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is ...
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Atmel ATmega48PA/88PA/168PA [Preliminary IDLE The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that chang- ing ...
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Assembly Code Example C Code Example Note: More advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 20.6 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is ...
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Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The following ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 20.6.3 Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) ...
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Receiving Frames with Data Bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCKn clock, and shifted ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an ...
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Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] 20.7.5 Parity Checker The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the ...
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Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Figure 20-6. Sampling of Data and Parity Bit RxD Sample (U2X = 0) 1 Sample 1 (U2X = 1) The decision of the logic level of the received bit is taken by doing a majority voting of ...
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The following equations can be used to calculate the ratio of the incoming data rate and inter- nal receiver baud rate slow Table 20-2 on page 192 error that can be tolerated. Note ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible sources for the receivers baud rate error. ...
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When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and waits for a new address frame from master. The process then repeats from 2. Using any of the 5- to ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] Table 20-5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864MHz osc Baud U2Xn = 0 Rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 ...
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Table 20-7. Baud Rate (bps) Max. Note: 20.11 Register Description 20.11.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Mod- ify-Write instructions (SBI and ...
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Bit 1 – U2Xn: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the ...
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Atmel ATmega48PA/88PA/168PA [Preliminary] • Bit 1 – RXB8n: Receive Data Bit 8 n RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits ...
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Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 20-10. USBS Bit Settings • Bit 2:1 – UCSZn1:0: Character Size The ...