ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 171

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

19.3
19.3.1
19.3.2
19.4
9223B–AVR–09/11
SS Pin Functionality
Data Modes
Slave Mode
Master Mode
When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is
held low, the SPI is activated, and MISO becomes an output if configured so by the user. All
other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which
means that it will not receive incoming data. Note that the SPI logic will be reset once the SS
pin is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the SS pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in the Shift Register.
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS
pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starting to send data to it. To avoid bus contention, the SPI system takes the follow-
ing actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a pos-
sibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If
the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI
Master mode.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
ure 19-3
edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly
seen by summarizing
19-2.
Table 19-2.
SPI Mode
the SPI becoming a Slave, the MOSI and SCK pins become inputs.
is set, the interrupt routine will be executed.
Atmel ATmega48PA/88PA/168PA [Preliminary]
0
1
2
3
and
Figure 19-4 on page
SPI Modes
Table 19-3 on page 173
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
Conditions
172. Data bits are shifted out and latched in on opposite
and
Sample (Falling)
Sample (Rising)
Leading Edge
Setup (Falling)
Setup (Rising)
Table 19-4 on page
173, as done in
Sample (Falling)
Sample (Rising)
Setup (Falling)
Trailing eDge
Setup (Rising)
Table
Fig-
171