ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 240

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

22.9
22.9.1
22.9.2
240
Register Description
Atmel ATmega48PA/88PA/168PA [Preliminary]
TWBR – TWI Bit Rate Register
TWCR – TWI Control Register
• Bits 7...0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a fre-
quency divider which generates the SCL clock frequency in the Master modes. See
Generator Unit” on page 220
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate
a Master access by applying a START condition to the bus, to generate a Receiver acknowl-
edge, to generate a stop condition, and to control halting of the bus while the data to be written
to the bus are written to the TWDR. It also indicates a write collision if data is attempted written
to TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application
software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the
TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The
TWINT Flag must be cleared by software by writing a logic one to it. Note that this flag is not
automatically cleared by hardware when executing the interrupt routine. Also note that clear-
ing this flag starts the operation of the TWI, so all accesses to the TWI Address Register
(TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete
before clearing this flag.
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to
one, the ACK pulse is generated on the TWI bus if the following conditions are met:
By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial
Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one
again.
Bit
(0xB8)
Read/Write
Initial Value
Bit
(0xBC)
Read/Write
Initial Value
1. The device’s own slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWAR is set.
3. A data byte has been received in Master Receiver or Slave Receiver mode.
TWBR7
TWINT
R/W
R/W
7
0
7
0
TWBR6
TWEA
R/W
R/W
6
0
6
0
for calculating bit rates.
TWBR5
TWSTA
R/W
R/W
5
0
5
0
TWBR4
TWSTO
R/W
R/W
4
0
4
0
TWBR3
TWWC
R/W
3
0
R
3
0
TWBR2
TWEN
R/W
R/W
2
0
2
0
TWBR1
R/W
1
0
R
1
–
0
TWBR0
TWIE
R/W
R/W
0
0
0
0
9223B–AVR–09/11
“Bit Rate
TWBR
TWCR